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Tomas Vanek ([email protected]) just uploaded a new patch set to Gerrit, which you 
can find at http://openocd.zylin.com/4290

-- gerrit

commit 7806c55897b71a5360cdccf6d0100fec0bce8e7b
Author: Tomas Vanek <[email protected]>
Date:   Sat Nov 4 09:54:07 2017 +0100

    target: add reset-halt event
    
    A configuration script may use a custom process to halt the target after
    reset.
    
    Change-Id: I2f2cd78d464d0ca4a2ab2e9181d70888371ea46e
    Signed-off-by: Tomas Vanek <[email protected]>

diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 3c5b797..5375d70 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -154,6 +154,32 @@ proc arp_reset_default_handler { phase target } {
        }
 }
 
+proc arp_reset_halt_default_handler { target } {
+       # Wait upto 1 second for target to halt.  Why 1sec? Cause
+       # the JTAG tap reset signal might be hooked to a slow
+       # resistor/capacitor circuit - and it might take a while
+       # to charge
+       catch { $target arp_waitstate halted 1000 }
+}
+
+# Utility to make 'reset halt' work as reset;halt on a target
+# It does not prevent running code after reset
+proc arp_reset_simple_halter { target } {
+       $target arp_poll
+       set st [$target curstate]
+       if { $st eq "reset" } {
+               # we assume running state follows
+               # if reset accidentaly halt, waiting is useless
+               catch { $target arp_waitstate running 1000 }
+               set st [$target curstate]
+       }
+       if { $st eq "running" } {
+               echo "$target: Ran after reset and before halt..."
+               $target arp_halt
+       }
+       arp_reset_halt_default_handler $target
+}
+
 proc ocd_process_reset_inner { MODE } {
        set targets [target names]
 
@@ -247,11 +273,7 @@ proc ocd_process_reset_inner { MODE } {
                                continue
                        }
 
-                       # Wait upto 1 second for target to halt.  Why 1sec? 
Cause
-                       # the JTAG tap reset signal might be hooked to a slow
-                       # resistor/capacitor circuit - and it might take a while
-                       # to charge
-                       catch { $t arp_waitstate halted 1000 }
+                       $t invoke-event reset-halt
 
                        # Did we succeed?
                        if { [$t curstate] ne "halted" } {
@@ -328,6 +350,7 @@ proc init_target_events {} {
                set_default_target_event $t reset-assert-pre 
"arp_reset_default_handler pre $t"
                set_default_target_event $t reset-assert-post 
"arp_reset_default_handler middle $t"
                set_default_target_event $t reset-deassert-post 
"arp_reset_default_handler post $t"
+               set_default_target_event $t reset-halt 
"arp_reset_halt_default_handler $t"
        }
 }
 
diff --git a/src/target/target.c b/src/target/target.c
index 046cdd4..d59abb5 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -208,6 +208,7 @@ static const Jim_Nvp nvp_target_event[] = {
        { .value = TARGET_EVENT_RESET_ASSERT_POST,   .name = 
"reset-assert-post" },
        { .value = TARGET_EVENT_RESET_DEASSERT_PRE,  .name = 
"reset-deassert-pre" },
        { .value = TARGET_EVENT_RESET_DEASSERT_POST, .name = 
"reset-deassert-post" },
+       { .value = TARGET_EVENT_RESET_HALT,          .name = "reset-halt" },
        { .value = TARGET_EVENT_RESET_INIT,          .name = "reset-init" },
        { .value = TARGET_EVENT_RESET_END,           .name = "reset-end" },
 
diff --git a/src/target/target.h b/src/target/target.h
index 1d12d24..40b0a6c 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -268,6 +268,7 @@ enum target_event {
        TARGET_EVENT_RESET_ASSERT_POST,
        TARGET_EVENT_RESET_DEASSERT_PRE,
        TARGET_EVENT_RESET_DEASSERT_POST,
+       TARGET_EVENT_RESET_HALT,
        TARGET_EVENT_RESET_INIT,
        TARGET_EVENT_RESET_END,
 

-- 

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