This is an automated email from Gerrit.

Jiri Kastner ([email protected]) just uploaded a new patch set to Gerrit, 
which you can find at http://openocd.zylin.com/4328

-- gerrit

commit 63a6a01f621c826cbc3af86d18babaa76e103fec
Author: Jiri Kastner <[email protected]>
Date:   Thu Jan 11 22:42:26 2018 +0100

    TODO: added ideas for improvement
    
    AVR32 (Nexus)
    PPC (Nexus, BDM)
    TriCore (Nexus, OCDS-L1)
    
    Change-Id: I6138c1daab88aba04403975bd5a45c73acc0afef
    Signed-off-by: Jiri Kastner <[email protected]>

diff --git a/TODO b/TODO
index aa43fdd..c9dfe09 100644
--- a/TODO
+++ b/TODO
@@ -111,6 +111,12 @@ TCP/IP packets handled by the server.
 
 - implement Serial Wire Debug interface
 
+@section thelistnexus Nexus Debug
+- implement Nexus Debug
+
+@section thelistsocds OCDS
+- implement On-Chip Debug Solution (OCDS-L1)
+
 @section thelistbs Boundary Scan Support
 
 - add STAPL support?
@@ -193,6 +199,13 @@ 
https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
   - incrementally improve working prototype in trunk. (SQ)
   - work out how to debug this target
   - AVR debugging protocol.
+- AVR32
+  - rework Nexus for other targets (PPC,TriCore)
+- PPC
+  - PPC with BDM support
+  - PPC with NEXUS
+- TriCore
+  - Aurix TC275 (OCDS-L1)
 - FPGA:
   - Altera Nios Soft-CPU support
 - Coldfire (suggested by NC)
@@ -298,6 +311,7 @@ These ideas were first introduced here: @par
 @subsection thelisttestgenerichw Generic Hardware Tester
 
 - implement VHDL to use for FPGA-based JTAG TAP testing device
+  - ice40, yosys
 - develop test suite that utilizes this testing device
 
 @section thelistautotools Autotools Build System

-- 

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