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Icenowy Zheng ([email protected]) just uploaded a new patch set to Gerrit, which 
you can find at http://openocd.zylin.com/4367

-- gerrit

commit 6b4547c85c770964d1a35056bf36b22ffe91d5c9
Author: Icenowy Zheng <[email protected]>
Date:   Sat Jan 20 04:30:51 2018 +0800

    target: add initial suport for several Allwinner SoCs
    
    Adds target config for three Allwinner SoC dies: Allwinner H3/H2+
    (called sun8iw7 by Allwinner, quad-core Cortex-A7), Allwinner V3/V3s
    (called sun8iw8 by Allwinner, single-core Cortex-A7) and Allwinner
    F1C100s/F1C600/R6 (called suniv by Allwinner, single-core ARM926EJ-S).
    
    All the SoCs has only a CPU in the JTAG chain.
    
    Change-Id: I7d1fc04fb8dd806ff2b30d8938431c71a81c6672
    Signed-off-by: Icenowy Zheng <[email protected]>

diff --git a/tcl/target/sun8i-h3.cfg b/tcl/target/sun8i-h3.cfg
new file mode 100644
index 0000000..1ba0f79
--- /dev/null
+++ b/tcl/target/sun8i-h3.cfg
@@ -0,0 +1,28 @@
+# Allwinner V3/V3s(sun8iw8) configuration
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME sun8iw7
+}
+ 
+# Subsidiary TAP: CoreSight Debug Access Port (DAP)
+if { [info exists DAP_TAPID ] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x5ba00477
+}
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+    -expected-id $_DAP_TAPID
+ 
+# GDB target:  Cortex-A, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+ 
+# SRAM-C: 44K at 0x00010000 (16K used : 0x10000~0x13fff);
+$_TARGETNAME configure -work-area-phys 0x00001000 -work-area-size 0x4000
+ 
+proc sun8iw7_dbginit {target} {
+     # General Cortex-A debug initialisation
+     cortex_a dbginit
+}
diff --git a/tcl/target/sun8i-v3.cfg b/tcl/target/sun8i-v3.cfg
new file mode 100644
index 0000000..c8895cc
--- /dev/null
+++ b/tcl/target/sun8i-v3.cfg
@@ -0,0 +1,28 @@
+# Allwinner V3/V3s(sun8iw8) configuration
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME sun8iw8
+}
+ 
+# Subsidiary TAP: CoreSight Debug Access Port (DAP)
+if { [info exists DAP_TAPID ] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x5ba00477
+}
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
+    -expected-id $_DAP_TAPID
+ 
+# GDB target:  Cortex-A, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+ 
+# SRAM-C: 44K at 0x00004000 (16K used : 0x8000~0xbfff);
+$_TARGETNAME configure -work-area-phys 0x00008000 -work-area-size 0x4000
+ 
+proc sun8iw8_dbginit {target} {
+     # General Cortex-A debug initialisation
+     cortex_a dbginit
+}
diff --git a/tcl/target/suniv.cfg b/tcl/target/suniv.cfg
new file mode 100644
index 0000000..9a6ccf8
--- /dev/null
+++ b/tcl/target/suniv.cfg
@@ -0,0 +1,36 @@
+# Target configuration for Allwinner new ARM9 SoCs
+# Processor       : ARM926ejs (wb) rev 0 (v4l)
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME suniv
+}
+
+if { [info exists ENDIAN] } {
+  set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+  set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+  set _CPUTAPID $CPUTAPID
+} else {
+  set _CPUTAPID 0x07926f0f
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 
$_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position 
$_TARGETNAME
+
+# FIX!!!!! should this really use srst_pulls_trst?
+# With srst_pulls_trst "reset halt" will not reset into the
+# halted mode, but rather "reset run" and then halt the target.
+#
+# However, without "srst_pulls_trst", then "reset halt" produces weird
+# errors:
+# WARNING: unknown debug reason: 0x0
+reset_config trst_and_srst

-- 

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