Hi,
It seems that this email should have gone to the list, but that failed
since I wasn't subscribed yet, so here it is again:
*[tickets:#175] <https://sourceforge.net/p/openocd/tickets/175/> ARM
disassemble BLX decoding wrong address*
*Status:* new
*Milestone:* 0.9.0
*Created:* Sun Jan 28, 2018 12:27 PM UTC by Philipp Gühring
*Last Updated:* Sun Jan 28, 2018 12:27 PM UTC
*Owner:* nobody
The BLX instruction seems to be decoded wrong in some places.
https://github.com/pfalcon/ScratchABit/issues/27#issuecomment-361054912
The file init.img is available here:
http://www2.futureware.at/~philipp/ssd/disasm.html
<http://www2.futureware.at/%7Ephilipp/ssd/disasm.html>
At the address 0x0000387a there is a BLX instruction in thumb mode with
the following bytes: 0xf00cebb4
openocd disassembled it as BLX 0x0000ffe6 (which would mean that the
target address must be in thumb mode since ARM addresses must be
divisible by 4)
But it seems that it should be BLX 0x0000ffe4 instead, and the target
code is actually ARM code, not thumb code.
The arm cortex_r4 core actually jumps from 0x0000387a->0x0000ffe4 so
ffe6 is definitley wrong.
In this form of the instruction, 6 is not possible because it has bit 1
set which is 0 by definition.
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