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-- gerrit
commit 69d74e6d65286ad4c732688e84a45d21786bc02b
Author: Forest Crossman <cyro...@gmail.com>
Date: Fri Feb 23 18:50:38 2018 -0600
tcl/target: Add config for MediaTek MT6797 (Helio X20)
Tested with the JTAG/SWD interface (CON9001) on the 96Boards MediaTek
X20 Consumer Edition development board.
Change-Id: I68a7412733e2b124e972d53526dade805bbdf101
Signed-off-by: Forest Crossman <cyro...@gmail.com>
diff --git a/tcl/target/mediatek/mt6797.cfg b/tcl/target/mediatek/mt6797.cfg
new file mode 100644
index 0000000..4fc14b1
--- /dev/null
+++ b/tcl/target/mediatek/mt6797.cfg
@@ -0,0 +1,56 @@
+# MediaTek MT6797 (Helio X20)
+#
+# This SoC has three main ARMv8 clusters: A 1.4 GHz Cortex-A53 cluster,
+# a 2.0 GHz Cortex-A53 cluster, and a 2.5 GHz Cortex-A72 cluster. These
+# clusters are in a big.LITTLE configuration for optimum performance and
+# power consumption.
+#
+# In addition to the ARMv8 clusters, this SoC also has a Cortex-M4
+# (typically used as a "sensor hub") and a Cortex-A9 (whose purpose is
+# currently unknown).
+
+source [find target/swj-dp.tcl]
+
+set _CHIPNAME mt6797
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x4ba00477
+}
+
+# declare the one JTAG/SWD tap to access the DAP
+swj_newdap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_DAP_TAPID -ignore-version -enable
+
+# declare the 4 Cortex-A53 cores in the 1.4 GHz cluster
+set _TARGETNAME $_CHIPNAME.a53.0.cpu
+target create ${_TARGETNAME}0 aarch64 -chain-position $_CHIPNAME.dap -coreid 0
-ctibase 0x80420000
+target create ${_TARGETNAME}1 aarch64 -chain-position $_CHIPNAME.dap -coreid 1
-ctibase 0x80520000 -defer-examine
+target create ${_TARGETNAME}2 aarch64 -chain-position $_CHIPNAME.dap -coreid 2
-ctibase 0x80620000 -defer-examine
+target create ${_TARGETNAME}3 aarch64 -chain-position $_CHIPNAME.dap -coreid 3
-ctibase 0x80720000 -defer-examine
+target smp ${_TARGETNAME}0 ${_TARGETNAME}1 ${_TARGETNAME}2 ${_TARGETNAME}3
+
+# declare the 4 Cortex-A53 cores in the 2.0 GHz cluster
+set _TARGETNAME $_CHIPNAME.a53.1.cpu
+target create ${_TARGETNAME}0 aarch64 -chain-position $_CHIPNAME.dap -coreid 4
-ctibase 0x80820000 -defer-examine
+target create ${_TARGETNAME}1 aarch64 -chain-position $_CHIPNAME.dap -coreid 5
-ctibase 0x80920000 -defer-examine
+target create ${_TARGETNAME}2 aarch64 -chain-position $_CHIPNAME.dap -coreid 6
-ctibase 0x80a20000 -defer-examine
+target create ${_TARGETNAME}3 aarch64 -chain-position $_CHIPNAME.dap -coreid 7
-ctibase 0x80b20000 -defer-examine
+target smp ${_TARGETNAME}0 ${_TARGETNAME}1 ${_TARGETNAME}2 ${_TARGETNAME}3
+
+# declare the 2 Cortex-A72 cores in the 2.5 GHz cluster
+set _TARGETNAME $_CHIPNAME.a72.cpu
+target create ${_TARGETNAME}0 aarch64 -chain-position $_CHIPNAME.dap -coreid 8
-ctibase 0x80c20000 -defer-examine
+target create ${_TARGETNAME}1 aarch64 -chain-position $_CHIPNAME.dap -coreid 9
-ctibase 0x80d20000 -defer-examine
+target smp ${_TARGETNAME}0 ${_TARGETNAME}1
+
+# declare the Cortex-A9
+set _TARGETNAME $_CHIPNAME.a9.cpu
+target create ${_TARGETNAME} cortex_a -chain-position $_CHIPNAME.dap
-defer-examine
+
+# declare the Cortex-M4 sensor hub
+set _TARGETNAME $_CHIPNAME.m4.cpu
+target create ${_TARGETNAME} cortex_m -chain-position $_CHIPNAME.dap
-defer-examine
--
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