On Wed, Apr 4, 2018 at 10:23 PM, Paul Fertser <[email protected]> wrote:
> Hello,
>
> On Wed, Apr 04, 2018 at 02:18:13PM -0700, Tim Newsome wrote:
> > Let's say I get my target in a state where examine() fails, but a reset
> would
> > revive it. It appears that OpenOCD can't do that, because until `init`
> has
> > completed, there is no `reset` command. Am I missing something? How
> should this
> > kind of situation be dealt with?
>
> Trying with "openocd -c 'interface dummy' -f target/stm32f1x.cfg" I
> see that in JTAG mode init actually completes, even when examine
> fails. SWD mode was added as a hack so it's a bit more complicated
> there but SWD is ARM-specific anyway.
>
Somehow I need to issue `reset halt` twice after `init` fails. The first
reset seems to be (mostly?) ignored. For now I'm saying that OpenOCD is
probably doing the right thing. There may be something wonky in the RISC-V
code that affects the first reset.
Thank you.
Tim
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