This is an automated email from Gerrit.

William D. Jones ([email protected]) just uploaded a new patch set to 
Gerrit, which you can find at http://openocd.zylin.com/4525

-- gerrit

commit c7a0ce64acd8146fefdb30f374cfc4d563f27f0e
Author: William D. Jones <[email protected]>
Date:   Tue May 15 18:05:02 2018 -0400

    tcl/board: Add Arty-S7 Spartan 7 FPGA Development Board
    
    Change-Id: I8bfe780cb67a1777d5112a68e8a9781bfe4f2038
    Signed-off-by: William D. Jones <[email protected]>

diff --git a/tcl/board/arty_s7.cfg b/tcl/board/arty_s7.cfg
new file mode 100644
index 0000000..563fb28
--- /dev/null
+++ b/tcl/board/arty_s7.cfg
@@ -0,0 +1,39 @@
+#
+# Arty S7: Spartan7 25/50 FPGA Board for Makers and Hobbyists
+#
+# https://www.xilinx.com/products/boards-and-kits/1-pnziih.html
+# 
https://store.digilentinc.com/arty-s7-spartan-7-fpga-board-for-makers-and-hobbyists/
+
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# Xilinx Spartan7-25/50 FPGA (XC7S{25,50}-CSGA324)
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+
+adapter_khz 25000
+
+# This configuration can only be used to load bitstreams either to the FPGA
+# via JTAG, or writing to an SPI flash via a jtagspi proxy. This configuration
+# cannot be used for debugging a target FPGA.
+#
+# Usage:
+#
+# Load Bitstream into FPGA:
+#    openocd -f board/arty_s7.cfg -c "init;\
+#    pld load 0 bitstream.bit;\
+#    shutdown"
+#
+# Write Bitstream to Flash:
+#    openocd -f board/arty_s7.cfg -c "init;\
+#    jtagspi_init 0 bscan_spi_xc7s??.bit;\
+#    jtagspi_program bitstream.bin 0;\
+#    xc7s_program xc7s.tap;\
+#    shutdown"
+#
+# jtagspi flash proxies can be found at:
+# https://github.com/quartiq/bscan_spi_bitstreams
+#
+# For the Spartan 50 variant, use
+#  - 
https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s50.bit
+# For the Spartan 25 variant, use
+#  - 
https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s25.bit

-- 

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