This is an automated email from Gerrit. Vladimir Neyelov ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4579
-- gerrit commit efa05b2a8f606129a00fb1dc3721909935d2140e Author: Vladimir Neyelov <[email protected]> Date: Wed Jun 27 08:45:01 2018 -0400 target/aarch64: There is no read/write access to SCTLR register in OpenOCD. This is implementation of “disable_mmu” command for aarch64 target. This command disable MMU and dcache in SCTLR register without cache flushing. Change-Id: I2c44b2077efc3a1d3f55f599edf2b4bb9019760f Signed-off-by: Vladimir Neyelov <[email protected]> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index df1e49c..b54d384 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -124,7 +124,7 @@ static int aarch64_restore_system_control_reg(struct target *target) /* modify system_control_reg in order to enable or disable mmu for : * - virt2phys address conversion * - read or write memory in phys or virt address */ -static int aarch64_mmu_modify(struct target *target, int enable) +static int aarch64_mmu_modify(struct target *target, int enable, int flush_dcache) { struct aarch64_common *aarch64 = target_to_aarch64(target); struct armv8_common *armv8 = &aarch64->armv8_common; @@ -144,8 +144,9 @@ static int aarch64_mmu_modify(struct target *target, int enable) /* data cache is active */ aarch64->system_control_reg_curr &= ~0x4U; /* flush data cache armv8 function to be called */ - if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache) - armv8->armv8_mmu.armv8_cache.flush_all_data_cache(target); + if (flush_dcache) + if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache) + armv8->armv8_mmu.armv8_cache.flush_all_data_cache(target); } if ((aarch64->system_control_reg_curr & 0x1U)) { aarch64->system_control_reg_curr &= ~0x1U; @@ -2101,7 +2102,7 @@ static int aarch64_read_phys_memory(struct target *target, if (count && buffer) { /* read memory through APB-AP */ - retval = aarch64_mmu_modify(target, 0); + retval = aarch64_mmu_modify(target, 0, 1); if (retval != ERROR_OK) return retval; retval = aarch64_read_cpu_memory(target, address, size, count, buffer); @@ -2122,7 +2123,7 @@ static int aarch64_read_memory(struct target *target, target_addr_t address, if (mmu_enabled) { /* enable MMU as we could have disabled it for phys access */ - retval = aarch64_mmu_modify(target, 1); + retval = aarch64_mmu_modify(target, 1, 0); if (retval != ERROR_OK) return retval; } @@ -2137,7 +2138,7 @@ static int aarch64_write_phys_memory(struct target *target, if (count && buffer) { /* write memory through APB-AP */ - retval = aarch64_mmu_modify(target, 0); + retval = aarch64_mmu_modify(target, 0, 1); if (retval != ERROR_OK) return retval; return aarch64_write_cpu_memory(target, address, size, count, buffer); @@ -2159,7 +2160,7 @@ static int aarch64_write_memory(struct target *target, target_addr_t address, if (mmu_enabled) { /* enable MMU as we could have disabled it for phys access */ - retval = aarch64_mmu_modify(target, 1); + retval = aarch64_mmu_modify(target, 1, 0); if (retval != ERROR_OK) return retval; } @@ -2545,6 +2546,13 @@ COMMAND_HANDLER(aarch64_handle_smp_off_command) return ERROR_OK; } +COMMAND_HANDLER(aarch64_handle_disable_mmu_command) +{ + struct target *target = get_current_target(CMD_CTX); + return aarch64_mmu_modify(target, 0, 0); +} + + COMMAND_HANDLER(aarch64_handle_smp_on_command) { struct target *target = get_current_target(CMD_CTX); @@ -2727,6 +2735,8 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv) return JIM_OK; } + + static const struct command_registration aarch64_exec_command_handlers[] = { { .name = "cache_info", @@ -2776,6 +2786,13 @@ static const struct command_registration aarch64_exec_command_handlers[] = { .help = "read coprocessor register", .usage = "cpnum op1 CRn CRm op2", }, + { + .name = "disable_mmu", + .handler = aarch64_handle_disable_mmu_command, + .mode = COMMAND_EXEC, + .help = "disable mmu and dcache in System Control Register", + .usage = "", + }, COMMAND_REGISTRATION_DONE -- ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
