This is an automated email from Gerrit. Antonio Borneo ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4679
-- gerrit commit f41f40151534a54f9322cf99a7d55dc7be6915cb Author: Antonio Borneo <[email protected]> Date: Fri Sep 21 15:52:02 2018 +0200 target/arm_adi_v5: fix sync CSW cache on apreg write Commit 0057c71ab6b81d0679b232318fc5f84b4becc471 updates the OpenOCD cached values of CSW and TAR registers if these registers are modified by an apreg command. The condition to force the update CSW is incorrect and it will erase the default CSW value. Fix it by erasing csw_value instead of csw_default to force the update Change-Id: I40273cb64d22ccfb9b6d3499bd39b586eb60de38 Fixes: 0057c71ab6b8 ("target/arm_adi_v5: sync CSW and TAR cache on apreg write") Signed-off-by: Antonio Borneo <[email protected]> diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index d9f3bd7..923bf77 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1738,7 +1738,7 @@ COMMAND_HANDLER(dap_apreg_command) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); switch (reg) { case MEM_AP_REG_CSW: - ap->csw_default = 0; /* invalid, force write */ + ap->csw_value = 0; /* invalid, force write */ retval = mem_ap_setup_csw(ap, value); break; case MEM_AP_REG_TAR: -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
