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Matthias Welwarsky ([email protected]) just uploaded a new patch set to 
Gerrit, which you can find at http://openocd.zylin.com/4691

-- gerrit

commit fb11dec5acc940f9f91c422a1f036682e8049392
Author: Matthias Welwarsky <[email protected]>
Date:   Mon Oct 1 14:05:39 2018 +0200

    aarch64: check if target core is powered down
    
    test EDPRSR.PU and skip target access if PU is low.
    
    Change-Id: I7aff4f19e77548d5fc8f4063c27977c1f0052f74
    Signed-off-by: Matthias Welwarsky <[email protected]>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 454de9e..9d39512 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -192,10 +192,22 @@ static int aarch64_init_debug_access(struct target 
*target)
 {
        struct armv8_common *armv8 = target_to_armv8(target);
        int retval;
-       uint32_t dummy;
+       uint32_t val;
 
        LOG_DEBUG("%s", target_name(target));
 
+       /* Clear Sticky Power Down status Bit in PRSR to enable access to
+          the registers in the Core Power Domain */
+       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+                                       armv8->debug_base + CPUV8_DBG_PRSR, 
&val);
+       if (retval != ERROR_OK)
+               return retval;
+
+       if (!(val & CPUV8_DBG_PRSR_PU)) {
+               LOG_WARNING("Target %s is powered down!", target_name(target));
+               return ERROR_OK;
+       }
+
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
                        armv8->debug_base + CPUV8_DBG_OSLAR, 0);
        if (retval != ERROR_OK) {
@@ -203,13 +215,6 @@ static int aarch64_init_debug_access(struct target *target)
                return retval;
        }
 
-       /* Clear Sticky Power Down status Bit in PRSR to enable access to
-          the registers in the Core Power Domain */
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUV8_DBG_PRSR, &dummy);
-       if (retval != ERROR_OK)
-               return retval;
-
        /*
         * Static CTI configuration:
         * Channel 0 -> trigger outputs HALT request to PE
@@ -2258,6 +2263,18 @@ static int aarch64_examine_first(struct target *target)
        } else
                armv8->debug_base = target->dbgbase;
 
+       /* Clear Sticky Power Down status Bit in PRSR to enable access to
+        * the registers in the Core Power Domain */
+       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+                                       armv8->debug_base + CPUV8_DBG_PRSR, 
&tmp0);
+       if (retval != ERROR_OK)
+               return retval;
+
+       if ((tmp0 & 0x01) /* EDPRSR.PU */ == 0) {
+               LOG_INFO("target %s is powered down!", target_name(target));
+               return ERROR_TARGET_INIT_FAILED;
+       }
+
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
                        armv8->debug_base + CPUV8_DBG_OSLAR, 0);
        if (retval != ERROR_OK) {
diff --git a/src/target/armv8.h b/src/target/armv8.h
index dfd54ed..b6a8ae3 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -262,7 +262,9 @@ static inline bool is_armv8(struct armv8_common *armv8)
 #define CPUV8_DBG_DSCR         0x088
 #define CPUV8_DBG_DRCR         0x090
 #define CPUV8_DBG_PRCR         0x310
+
 #define CPUV8_DBG_PRSR         0x314
+#define CPUV8_DBG_PRSR_PU      0x01
 
 #define CPUV8_DBG_DTRRX                0x080
 #define CPUV8_DBG_ITR          0x084

-- 


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