This is an automated email from Gerrit. Leonard Crestez ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5034
-- gerrit commit 32d34295d4cce73219f3499b7a90e66fe66d1fab Author: Leonard Crestez <[email protected]> Date: Fri Aug 10 19:54:43 2018 +0300 target/imx6: Add all TAPIDs Copy all SJC TAPIPs from imx reference manuals. Some imx6 chips are based on Cortex-A7; did not check that they actually work with this base config. Change-Id: I3b07d94058c2c5e6313cfc8bb43134a90682a62e Signed-off-by: Leonard Crestez <[email protected]> diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg index 58dc418..ac5987b 100644 --- a/tcl/target/imx6.cfg +++ b/tcl/target/imx6.cfg @@ -20,19 +20,42 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f # System JTAG Controller + +# Supported SJC TAPIDs from imx reference manuals: +set _SJC_TAPID_6Q 0x0191c01d +set _SJC_TAPID_6D 0x0191e01d +set _SJC_TAPID_6QP 0x3191c01d +set _SJC_TAPID_6DP 0x3191d01d +set _SJC_TAPID_6DL 0x0891a01d +set _SJC_TAPID_6S 0x0891b01d +set _SJC_TAPID_6SX 0x0891c01d +set _SJC_TAPID_6SL 0x0891f01d +set _SJC_TAPID_6SLL 0x088c201d +set _SJC_TAPID_6UL 0x0891d01d +set _SJC_TAPID_6ULL 0x0891e01d +set _SJC_TAPID_6ULZ 0x1891e01d + +# Allow external override of the first SJC TAPID if { [info exists SJC_TAPID] } { set _SJC_TAPID $SJC_TAPID } else { - set _SJC_TAPID 0x0191c01d + set _SJC_TAPID $_SJC_TAPID_6Q } -set _SJC_TAPID2 0x2191c01d -set _SJC_TAPID3 0x2191e01d -set _SJC_TAPID4 0x1191c01d jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ -ignore-version \ - -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \ - -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4 + -expected-id $_SJC_TAPID \ + -expected-id $_SJC_TAPID_6QP \ + -expected-id $_SJC_TAPID_6DP \ + -expected-id $_SJC_TAPID_6D \ + -expected-id $_SJC_TAPID_6DL \ + -expected-id $_SJC_TAPID_6S \ + -expected-id $_SJC_TAPID_6SX \ + -expected-id $_SJC_TAPID_6SL \ + -expected-id $_SJC_TAPID_6SLL \ + -expected-id $_SJC_TAPID_6UL \ + -expected-id $_SJC_TAPID_6ULL \ + -expected-id $_SJC_TAPID_6ULZ \ # GDB target: Cortex-A9, using DAP, configuring only one core # Base addresses of cores: -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
