This is an automated email from Gerrit. Leonard Crestez ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5037
-- gerrit commit ab0c07299f9d94f1a32765629ec9804bea89410f Author: Leonard Crestez <[email protected]> Date: Wed Apr 3 21:32:17 2019 +0300 target/imx8x: Initial support Tested on imx8qxp-mek board running linux Change-Id: Iad72668a706775d9f5557f43660ccfa22ea90a19 Signed-off-by: Leonard Crestez <[email protected]> diff --git a/tcl/target/imx8x.cfg b/tcl/target/imx8x.cfg new file mode 100644 index 0000000..1fda52f --- /dev/null +++ b/tcl/target/imx8x.cfg @@ -0,0 +1,76 @@ +# +# NXP i.MX8X family +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx8x +} + +# Default to 4 core (for imx8qxp) +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 4 +} + +# CoreSight Debug Access Port (DAP) +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + # TAPID is from FreeScale! + set _DAP_TAPID 0x1890201d +} + +jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \ + -expected-id $_DAP_TAPID + +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap + +# AXI: Main SOC bus on AP #0 +target create ${_CHIPNAME}.axi mem_ap -dap ${_CHIPNAME}.dap -ap-num 0 + +# Up to 4x Cortex-A35 on AP #4 +set _TARGETNAME $_CHIPNAME.a35 +set _CTINAME $_CHIPNAME.cti + +set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000} +set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000} + +for { set _core 0 } { $_core < $_cores } { incr _core } { + cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 4 \ + -ctibase [lindex $CTIBASE $_core] + + set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core" + + if { $_core != 0 } { + # non-boot core examination may fail + set _command "$_command -defer-examine" + set _smp_command "$_smp_command $_TARGETNAME.$_core" + } else { + set _smp_command "target smp $_TARGETNAME.$_core" + } + + eval $_command +} + +eval $_smp_command + +# SCU: Cortex-M4 core +# always running imx SC firmware +target create ${_CHIPNAME}.scu cortex_m -dap ${_CHIPNAME}.dap -ap-num 1 + +# AHB from SCU perspective +target create ${_CHIPNAME}.scu_ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 1 + +# Cortex-M4 core on AP #2 (default off) +target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 2 \ + -defer-examine + +# Debug APB bus +target create ${_CHIPNAME}.apb mem_ap -dap ${_CHIPNAME}.dap -ap-num 4 + +# Default target is boot core a35.0 +targets $_CHIPNAME.a35.0 -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
