This is an automated email from Gerrit.
Tommy Vestermark (t...@vestermark.dk) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/5103
-- gerrit
commit 903ef9311fc7bd47a51950f2cb479600b678d045
Author: Tommy Vestermark <t...@vestermark.dk>
Date: Thu Apr 11 13:28:48 2019 +1000
cortex_a: Add support for Cortex R5
Unlock debug via LSR/LAR registers.
(Commit 0a2f1b29 introduced bug that will lock Cortex R4/R5 from APB
access making debug impossible.)
- ARM DDI0460D Cortex-R5 Technical Reference Manual section 12.5
- ARM DDI0363G Cortex-R4 Technical Reference Manual section 12.5
Improve parsing of MPIDR register to avoid error message for Cortex R5
- ARM DDI0460D Cortex-R5 Technical Reference Manual section 4.3.6
- ARM 100048_0002_0 Cortex-A73 Technical Reference Manual section 4.5.2
Tested on: TMS570LC4357
Change-Id: I6c684613b0faaccb01291c35dbcdfa9b4bc69712
Signed-off-by: Tommy Vestermark <t...@vestermark.dk>
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 437a2f2..0d591f8 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -307,23 +307,20 @@ static int armv7a_read_mpidr(struct target *target)
if (retval != ERROR_OK)
goto done;
- /* ARMv7R uses a different format for MPIDR.
- * When configured uniprocessor (most R cores) it reads as 0.
- * This will need to be implemented for multiprocessor ARMv7R cores. */
- if (armv7a->is_armv7r) {
- if (mpidr)
- LOG_ERROR("MPIDR nonzero in ARMv7-R target");
- goto done;
- }
-
if (mpidr & 1<<31) {
+ LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
armv7a->multi_processor_system = (mpidr >> 30) & 1;
+ armv7a->multi_threading_processor = (mpidr >> 24) & 1;
+ armv7a->level2_id = (mpidr >> 16) & 0xf;
armv7a->cluster_id = (mpidr >> 8) & 0xf;
- armv7a->cpu_id = mpidr & 0x3;
- LOG_INFO("%s cluster %x core %x %s", target_name(target),
+ armv7a->cpu_id = mpidr & 0xf;
+ LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s",
+ target_name(target),
+ armv7a->level2_id,
armv7a->cluster_id,
armv7a->cpu_id,
- armv7a->multi_processor_system == 0 ? "multi core" :
"mono core");
+ armv7a->multi_processor_system == 0 ? "multi core" :
"mono core",
+ armv7a->multi_threading_processor == 1 ? "SMT" : "no
SMT");
} else
LOG_ERROR("MPIDR not in multiprocessor format");
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 1e88c98..577abcb 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -108,6 +108,8 @@ struct armv7a_common {
struct adiv5_ap *debug_ap;
/* mdir */
uint8_t multi_processor_system;
+ uint8_t multi_threading_processor;
+ uint8_t level2_id;
uint8_t cluster_id;
uint8_t cpu_id;
bool is_armv7r;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 6eb6aa9..77e1211 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -203,13 +203,6 @@ static int cortex_a_init_debug_access(struct target
*target)
uint32_t dscr;
int retval;
- /* lock memory-mapped access to debug registers to prevent
- * software interference */
- retval = mem_ap_write_u32(armv7a->debug_ap,
- armv7a->debug_base + CPUDBG_LOCKACCESS, 0);
- if (retval != ERROR_OK)
- return retval;
-
/* Disable cacheline fills and force cache write-through in debug state
*/
retval = mem_ap_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCCR, 0);
@@ -2641,7 +2634,7 @@ static int cortex_a_examine_first(struct target *target)
int i;
int retval = ERROR_OK;
- uint32_t didr, cpuid, dbg_osreg;
+ uint32_t didr, cpuid, dbg_osreg, dbg_lsr;
/* Search for the APB-AP - it is needed for access to debug registers */
retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
@@ -2746,6 +2739,37 @@ static int cortex_a_examine_first(struct target *target)
}
}
+ /* Read DBGLSR and check if Debug Lock is implemented */
+ /* See Cortex-R5 Tech Ref Manual section 12.3.8 */
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_LOCKSTATUS,
&dbg_lsr);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("target->coreid %" PRId32 " DBGLSR 0x%" PRIx32,
target->coreid, dbg_lsr);
+
+ /* check if Debug Lock is implemented */
+ if ((dbg_lsr & LSR_LOCK_IMPLEMENTED) == LSR_LOCK_IMPLEMENTED) {
+ /* check if OS Lock is set */
+ if (dbg_lsr & LSR_LOCKED) {
+ LOG_DEBUG("target->coreid %" PRId32 " Debug Lock set!
Trying to unlock", target->coreid);
+
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base +
CPUDBG_LOCKACCESS,
+ LAR_KEY);
+ if (retval == ERROR_OK)
+ retval =
mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base +
CPUDBG_LOCKSTATUS, &dbg_lsr);
+
+ /* if we fail to access the register or cannot reset
the LOCKED bit, bail out */
+ if (retval != ERROR_OK || (dbg_lsr & LSR_LOCKED) != 0) {
+ LOG_ERROR("target->coreid %" PRId32 " Debug
LOCKED sticky, core not powered?",
+ target->coreid);
+ target->state = TARGET_UNKNOWN; /*
TARGET_NO_POWER? */
+ return ERROR_TARGET_INIT_FAILED;
+ }
+ }
+ }
+
armv7a->arm.core_type = ARM_MODE_MON;
/* Avoid recreating the registers cache */
diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h
index 197a599..74766dc 100644
--- a/src/target/cortex_a.h
+++ b/src/target/cortex_a.h
@@ -48,6 +48,14 @@
#define CPUDBG_LOCKSTATUS 0xFB4
#define CPUDBG_OSLAR_LK_MASK (1 << 1)
+/* LAR (Lock Access Register) bits */
+#define LAR_KEY (0xC5ACCE55)
+
+/* LSR (Lock Status Register) bits */
+#define LSR_LOCK_IMPLEMENTED (1 << 0)
+#define LSR_LOCKED (1 << 1)
+
+
#define BRP_NORMAL 0
#define BRP_CONTEXT 1
--
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