This is an automated email from Gerrit.
Matthias Welwarsky (matth...@welwarsky.de) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/5105
-- gerrit
commit 5d8fdf54f30ff9cb818db65008118bb0f9e30884
Author: Matthias Welwarsky <matthias.welwar...@sysgo.com>
Date: Thu Apr 11 10:22:27 2019 +0200
cortex_a: warn on broken debug_base setting
A common problem with target configurations appears to be broken
debug base address configuration. ADIv5 specifies that bit 31 of
the debug base address serves as identification of an external
debugger, as opposed to an internal access to memory mapped debug
registers by the CPU. External accesses are treated as privileged
and require no debug authentification via the lock access register.
Sometimes the base address of a debug component is wrong even
in the targets' ROM table. In this case, the correct base address
must be specified using the -dbgbase argument when creating the
target.
This patch adds a warning when bit 31 of the debug base address
is not set, as a hint to the user.
Change-Id: I9c41d85a138123c657ef655e3436a2aa39249dcc
Signed-off-by: Matthias Welwarsky <matthias.welwar...@sysgo.com>
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 6eb6aa9..fb9a806 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2681,6 +2681,10 @@ static int cortex_a_examine_first(struct target *target)
} else
armv7a->debug_base = target->dbgbase;
+ if ((armv7a->debug_base & (1UL<<31)) == 0)
+ LOG_WARNING("Debug base address for target %s has bit 31 set to
0. Access to debug registers will likely fail!\n"
+ "Please fix the target configuration.",
target_name(target));
+
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DIDR, &didr);
if (retval != ERROR_OK) {
--
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