This is an automated email from Gerrit.

Leonard Crestez (leonard.cres...@nxp.com) just uploaded a new patch set to 
Gerrit, which you can find at http://openocd.zylin.com/5125

-- gerrit

commit 19415c6b8a323a7eeff6c7aeac5db23c72c9aa0a
Author: Leonard Crestez <leonard.cres...@nxp.com>
Date:   Tue Apr 16 23:30:32 2019 +0300

    arm_adi_v5: Initialize csw_default based on IDR
    
    The implementation-defined bits of CSW have different semantics and
    different recommended defaults based on bus type. Initialize csw_default
    based on IDR instead of hardcoding to AHB.
    
    Change-Id: I447cd52aa5b6d8fadab413e88a073d5e311bf616
    Signed-off-by: Leonard Crestez <leonard.cres...@nxp.com>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 6c25bcc..c6c33f1 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -741,7 +741,7 @@ int dap_dp_init(struct adiv5_dap *dap)
 int mem_ap_init(struct adiv5_ap *ap)
 {
        /* check that we support packed transfers */
-       uint32_t csw, cfg;
+       uint32_t csw, cfg, idr;
        int retval;
        struct adiv5_dap *dap = ap->dap;
 
@@ -759,10 +759,45 @@ int mem_ap_init(struct adiv5_ap *ap)
        if (retval != ERROR_OK)
                return retval;
 
+       retval = dap_queue_ap_read(ap, AP_REG_IDR, &idr);
+       if (retval != ERROR_OK)
+               return retval;
+
        retval = dap_run(dap);
        if (retval != ERROR_OK)
                return retval;
 
+       LOG_DEBUG("MEM_AP %d: IDR=0x%08" PRIX32 " CFG=0x%08" PRIX32,
+                       ap->ap_num, idr, cfg);
+
+       /* Initialize mem_ap csw_default based on bus type. */
+       if ((idr & IDR_CLASS) == AP_CLASS_MEM_AP) {
+               if ((idr & IDR_JEP106) == IDR_JEP106_ARM &&
+                               (idr & IDR_TYPE) == AP_TYPE_AHB_AP) {
+                       LOG_DEBUG("MEM_AP %d recognized as AHB", ap->ap_num);
+                       ap->csw_reset_default = CSW_AHB_DEFAULT;
+               } else if ((idr & IDR_JEP106) == IDR_JEP106_ARM &&
+                               (idr & IDR_TYPE) == AP_TYPE_AXI_AP) {
+                       LOG_DEBUG("MEM_AP %d recognized as AXI", ap->ap_num);
+                       ap->csw_reset_default = CSW_AXI_DEFAULT;
+               } else if ((idr & IDR_JEP106) == IDR_JEP106_ARM &&
+                               (idr & IDR_TYPE) == AP_TYPE_APB_AP) {
+                       LOG_DEBUG("MEM_AP %d recognized as APB", ap->ap_num);
+                       ap->csw_reset_default = CSW_APB_DEFAULT;
+               } else {
+                       /* CSW.Prot and CSW.Type must reset to a valid access
+                        * type and ARM strongly recommends that these bits are
+                        * reset to a useful access type
+                        */
+                       ap->csw_reset_default = csw & 0xFFFFF000;
+                       LOG_WARNING("MEM_AP %d unrecognized, use reset CSW from 
hardware",
+                                       ap->ap_num);
+               }
+               ap->csw_default = ap->csw_reset_default;
+               LOG_DEBUG("MEM_AP %d initialized default reset CSW 0x%08" 
PRIX32,
+                               ap->ap_num, ap->csw_default);
+       }
+
        if (csw & CSW_ADDRINC_PACKED)
                ap->packed_transfers = true;
        else
@@ -1745,7 +1780,7 @@ COMMAND_HANDLER(dap_apcsw_command)
                return ERROR_OK;
        case 1:
                if (strcmp(CMD_ARGV[0], "default") == 0)
-                       csw_val = CSW_AHB_DEFAULT;
+                       csw_val = dap->ap[dap->apsel].csw_reset_default;
                else
                        COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
 
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 9ca2966..86aac8b 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -179,6 +179,12 @@ struct adiv5_ap {
        uint32_t csw_default;
 
        /**
+        * Default reset value for (MEM-AP) AP_REG_CSW register.
+         * Based on IDR or value read from HW
+        */
+       uint32_t csw_reset_default;
+
+       /**
         * Cache for (MEM-AP) AP_REG_CSW register value.  This is written to
         * configure an access mode, such as autoincrementing AP_REG_TAR during
         * word access.  "-1" indicates no cached value.
diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c
index 17a8208..bb6e7f8 100644
--- a/src/target/arm_dap.c
+++ b/src/target/arm_dap.c
@@ -55,8 +55,9 @@ static void dap_instance_init(struct adiv5_dap *dap)
                dap->ap[i].memaccess_tck = 255;
                /* Number of bits for tar autoincrement, impl. dep. at least 10 
*/
                dap->ap[i].tar_autoincr_block = (1<<10);
-               /* default CSW value */
-               dap->ap[i].csw_default = CSW_AHB_DEFAULT;
+               /* default CSW values at mem_ap_init time */
+               dap->ap[i].csw_default = 0xFFFFFFFF;
+               dap->ap[i].csw_reset_default = 0xFFFFFFFF;
        }
        INIT_LIST_HEAD(&dap->cmd_journal);
 }

-- 


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