This is an automated email from Gerrit. Tarek BOCHKATI ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5130
-- gerrit commit 4930f455223014e2c2b2efec148cbec48064cfb5 Author: Tarek BOCHKATI <[email protected]> Date: Tue Apr 23 17:13:33 2019 +0200 tcl/target/stm32h7x: add support of dual core variant of STM32H7 STM32H7x7 and STM32H7x5 devices contains two cores : CM7 + CM4 Once the second core is detected it gets examined. Note: since HLA adapters does not support multi access port, then when hla is used only Cortex-M7 target is created Change-Id: Iad9c30826965ddb9be5dee628bc2e63f953bbcb8 Signed-off-by: Tarek BOCHKATI <[email protected]> diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg index 0bfc43d..7d47afa 100644 --- a/tcl/target/stm32h7x.cfg +++ b/tcl/target/stm32h7x.cfg @@ -40,13 +40,21 @@ if {[using_jtag]} { swj_newdap $_CHIPNAME bs -irlen 5 } -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap +if {![using_hla]} { + target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0 + target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3 -defer-examine + target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2 +} else { + # multi AP is not supported using hla + target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap +} + +targets $_CHIPNAME.cpu0 -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 +$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0 # Clock after reset is HSI at 64 MHz, no need of PLL adapter_khz 1800 @@ -83,7 +91,7 @@ if {![using_hla]} { $_CHIPNAME.dap apcsw 0x08000000 0x08000000 } -$_TARGETNAME configure -event examine-end { +$_CHIPNAME.cpu0 configure -event examine-end { # Enable D3 and D1 DBG clocks # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN mmw 0x5C001004 0x00600000 0 @@ -97,16 +105,26 @@ $_TARGETNAME configure -event examine-end { mmw 0x5C001034 0x00000040 0 # DBGMCU_APB4FZ1 |= WDGLSD1 mmw 0x5C001054 0x00040000 0 + + # Check if Cortex-M4 is present (bit 16 of chip options register from SYSCFG) + # RCC_APB4ENR |= SYSCFGEN + mmw 0x580244F4 0x00000002 0 + $_CHIPNAME.cpu0 mem2array chip_options 32 0x58000500 1 + if {$chip_options(0) & 0x10000} { + if {![using_hla]} { + $_CHIPNAME.cpu1 arp_examine + } + } } -$_TARGETNAME configure -event trace-config { +$_CHIPNAME.cpu0 configure -event trace-config { # Set TRACECLKEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0x5C001004 0x00100000 0 } -$_TARGETNAME configure -event reset-init { +$_CHIPNAME.cpu0 configure -event reset-init { # Clock after reset is HSI at 64 MHz, no need of PLL adapter_khz 4000 } -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
