This is an automated email from Gerrit.
Aurélien Martin (martau...@gmail.com) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/5266
-- gerrit
commit 9a70c67269925a8dda9440106714dc8bb266cddf
Author: Aurélien Martin <martau...@gmail.com>
Date: Mon Jul 22 23:13:29 2019 +0200
nrf5: Refresh the watchdog while flashing
If watchdog is enabled, there's no way we can disable it while the flashing
firmware
is running. (Halt disables it, but software reset doesn't.) So let's have
the flashing
firmware refresh the watchdog regularly, in case it has been enabled by
previously
running software. Failure to do so could lead to a watchdog reset in the
middle of
the chip bieng programmed.
Change-Id: I79d41593948aae0080480e891552e1c2ee3ccbd0
Signed-off-by: Aurélien Martin <martau...@gmail.com>
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 4041bfb..e819d65 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -622,24 +622,29 @@ static int nrf5_erase_page(struct flash_bank *bank,
static const uint8_t nrf5_flash_write_code[] = {
/* See contrib/loaders/flash/cortex-m0.S */
/* <wait_fifo>: */
+ 0x3e, 0x60, /* str r6, [r7, #0] */
0x0d, 0x68, /* ldr r5, [r1, #0] */
0x00, 0x2d, /* cmp r5, #0 */
- 0x0b, 0xd0, /* beq.n 1e <exit> */
+ 0x0b, 0xd0, /* beq.n 24 <exit> */
0x4c, 0x68, /* ldr r4, [r1, #4] */
0xac, 0x42, /* cmp r4, r5 */
- 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
+ 0xf8, 0xd0, /* beq.n 4 <wait_fifo> */
0x20, 0xcc, /* ldmia r4!, {r5} */
0x20, 0xc3, /* stmia r3!, {r5} */
0x94, 0x42, /* cmp r4, r2 */
- 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
+ 0x01, 0xd3, /* bcc.n 1e <no_wrap> */
0x0c, 0x46, /* mov r4, r1 */
0x08, 0x34, /* adds r4, #8 */
/* <no_wrap>: */
0x4c, 0x60, /* str r4, [r1, #4] */
0x04, 0x38, /* subs r0, #4 */
- 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
+ 0xef, 0xd1, /* bne.n 0 <wait_fifo> */
/* <exit>: */
- 0x00, 0xbe /* bkpt 0x0000 */
+ 0x00, 0xbe, /* bkpt 0x0000 */
+ 0xc0, 0x46, /* nop */
+ /* <data>: */
+ 0x35, 0x46, 0x52, 0x6e, /* Watchdog magic value */
+ 0x00, 0x06, 0x01, 0x40, /* Watchdog refresh register */
};
--
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