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Tomas Vanek ([email protected]) just uploaded a new patch set to Gerrit, which you 
can find at http://openocd.zylin.com/5376

-- gerrit

commit 4980cf6ddd1d550d0b288c0118997f0650c3277d
Author: Tomas Vanek <[email protected]>
Date:   Fri Dec 20 23:43:55 2019 +0100

    target/arm946e: add missing error detection
    
    Discoverd by clang static analyzer.
    While on it remove useless type casts from arm946e_read_cp15() parameter.
    
    Change-Id: I549e19685b431400243800ee0f7d1bbe6cdb14b4
    Signed-off-by: Tomas Vanek <[email protected]>

diff --git a/src/target/arm946e.c b/src/target/arm946e.c
index 112631a..4ef167a 100644
--- a/src/target/arm946e.c
+++ b/src/target/arm946e.c
@@ -267,7 +267,11 @@ uint32_t arm946e_invalidate_whole_dcache(struct target 
*target)
 
                        /* Read dtag */
                        uint32_t dtag;
-                       arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
+                       retval = arm946e_read_cp15(target, 0x16, &dtag);
+                       if (retval != ERROR_OK) {
+                               LOG_DEBUG("ERROR reading dtag");
+                               return retval;
+                       }
 
                        /* Check cache line VALID bit */
                        if (!(dtag >> 4 & 0x1))
@@ -321,7 +325,7 @@ int arm946e_post_debug_entry(struct target *target)
 
        /* See if CACHES are enabled, and save that info
         * in the context bits, so that arm946e_pre_restore_context() can use 
them */
-       arm946e_read_cp15(target, CP15_CTL, (uint32_t *) &ctr_reg);
+       arm946e_read_cp15(target, CP15_CTL, &ctr_reg);
 
        /* Save control reg in the context */
        arm946e->cp15_control_reg = ctr_reg;
@@ -362,7 +366,7 @@ void arm946e_pre_restore_context(struct target *target)
        if (arm946e_preserve_cache) {
                struct arm946e_common *arm946e = target_to_arm946(target);
                /* Get the contents of the CTR reg */
-               arm946e_read_cp15(target, CP15_CTL, (uint32_t *) &ctr_reg);
+               arm946e_read_cp15(target, CP15_CTL, &ctr_reg);
 
                /**
                 * Read-modify-write CP15 control
@@ -410,7 +414,11 @@ uint32_t arm946e_invalidate_dcache(struct target *target, 
uint32_t address,
                        }
 
                        /* Read dtag */
-                       arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
+                       retval = arm946e_read_cp15(target, 0x16, &dtag);
+                       if (retval != ERROR_OK) {
+                               LOG_DEBUG("ERROR reading dtag");
+                               return retval;
+                       }
 
                        /* Check cache line VALID bit */
                        if (!(dtag >> 4 & 0x1))
@@ -463,7 +471,11 @@ uint32_t arm946e_invalidate_icache(struct target *target, 
uint32_t address,
                        }
 
                        /* Read itag */
-                       arm946e_read_cp15(target, 0x17, (uint32_t *) &itag);
+                       retval = arm946e_read_cp15(target, 0x17, &itag);
+                       if (retval != ERROR_OK) {
+                               LOG_DEBUG("ERROR reading itag");
+                               return retval;
+                       }
 
                        /* Check cache line VALID bit */
                        if (!(itag >> 4 & 0x1))

-- 


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