On Fri, Apr 3, 2020 at 2:58 PM Jan Matyáš <jmat...@codasip.com> wrote: > > >> > On 3 Apr 2020, at 12:37, Tommy Murphy <tommy_mur...@hotmail.com> wrote: >> > >> > OpenOCD to debug against simulated targets including RISC-V simulated >> > using Verilator and Spike >> >> Yes, this might be a solution, but I first have to make this simulator run >> on all my target platforms (Win 32/64, Linux Intel 32/64, Linux Arm 32/64, >> macOS 64, which might be a project larger than maintaining the OpenOCD xPack >> itself. >> >> I was looking for a simpler solution, something internally used to test >> OpenOCD, if available. >> > > If simplicity is desired and at the same time you would like to have a "real > enough" target to exercise basic OpenOCD functionality (halt, > single-stepping, breakpoints, access to memory and registers ...), I would > personally recommend an instruction set simulator as the target. (As opposed > to tinkering with RTL designs, Verilator, etc.) > > As I am only familiar with RISC-V, I would recommend giving Spike ISS a try. > > The use instructions for Spike are simple. Just omit the part dealing with > GDB: > https://github.com/riscv/riscv-isa-sim#debugging-with-gdb
Cool! Remote bitbang for external OpenOCD connection! Maybe a little slow (at the end it's a bitbang!) but should be fine. I'll give a try. Spike is already available for Arch Linux. In the past I investigated about Qemu, but it only provides a remote-gdb port, nothing that can be used (today) by openocd. Antonio > The build instructions for Spike are also simple enough, but I am wondering > if there are any further "hidden" dependencies, not apparent from the README. > That would of course make it more complicated to target your wide range of > platforms. Haven't worked with Spike for some time. _______________________________________________ OpenOCD-devel mailing list OpenOCD-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openocd-devel
