This is an automated email from Gerrit.
Daniel Goehring (dgoeh...@os.amperecomputing.com) just uploaded a new patch set
to Gerrit, which you can find at http://openocd.zylin.com/5569
-- gerrit
commit f74e17476a330e430e0d58fbe114b13db34a8b9a
Author: Anthony Ferranti <ferra...@os.amperecomputing.com>
Date: Wed Apr 1 15:46:30 2020 -0400
eMAG: Add Ampere eMAG config files
Add board and target configuration files for
Ampere eMAG8180 board and Ampere eMAG processor.
Tested on an Ampere eMAG8180 development platform.
Change-Id: I222653f0fc12d25202a7e469db3594076cbc38ed
Signed-off-by: Anthony Ferranti <ferra...@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoeh...@os.amperecomputing.com>
diff --git a/tcl/board/ampere_emag8180.cfg b/tcl/board/ampere_emag8180.cfg
new file mode 100644
index 0000000..f29e187
--- /dev/null
+++ b/tcl/board/ampere_emag8180.cfg
@@ -0,0 +1,39 @@
+#
+# OpenOCD Board Configuration for eMAG Development Platform
+#
+# Copyright (c) 2019-2020, Ampere Computing LLC
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program;
+#
+#
+
+#
+# Configure JTAG speed
+#
+
+adapter speed 2000
+
+#
+# Configure Resets
+#
+
+adapter srst delay 200
+jtag_ntrst_delay 100
+reset_config trst_only
+
+#
+# Configure Targets
+#
+
+source [find target/ampere_emag.cfg]
diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg
new file mode 100644
index 0000000..792bc12
--- /dev/null
+++ b/tcl/target/ampere_emag.cfg
@@ -0,0 +1,112 @@
+#
+# OpenOCD Target Configuration for eMAG ARMv8 Processor
+#
+# Copyright (c) 2019-2020, Ampere Computing LLC
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program;
+#
+#
+
+#
+# Configure defaults for target
+# Can be overriden in board configuration file
+#
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME ${CHIPNAME}
+} else {
+ set _CHIPNAME emag
+}
+
+if { [info exists NUMCORES] } {
+ set _NUMCORES ${NUMCORES}
+} else {
+ set _NUMCORES 32
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN ${ENDIAN}
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID ${CPUTAPID}
+} else {
+ set _CPUTAPID 0x4BA00477
+}
+
+#
+# Configure JTAG TAP
+#
+
+jtag newtap ${_CHIPNAME} cpu -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id
$_CPUTAPID
+set _TAPNAME ${_CHIPNAME}.cpu
+
+set _DAPNAME ${_TAPNAME}_dap
+set _APNUM 1
+dap create ${_DAPNAME} -chain-position ${_TAPNAME}
+${_DAPNAME} apsel ${_APNUM}
+
+# Create the DAP AP0 MEM-AP AHB-AP target
+target create AHB mem_ap -endian $_ENDIAN -dap ${_DAPNAME} -ap-num 0
+
+# Create the DAP AP1 MEM-AP APB-AP target
+target create APB mem_ap -endian $_ENDIAN -dap ${_DAPNAME} -ap-num 1
+
+#
+# Configure target CPUs
+#
+
+# Build string used to enable smp mode
+set _SMP_STR "target smp"
+
+for {set _i 0} {$_i < $_NUMCORES} {incr _i} {
+ # Configure which TAP to use
+ eval [format "set _TARGETNAME ${_TAPNAME}_%02d" $_i]
+
+ # Create and configure Cross Trigger Interface (CTI) - required for
halt and resume
+ set _CTINAME ${_TARGETNAME}.cti
+ eval [format "cti create ${_CTINAME} -dap ${_DAPNAME} -ap-num ${_APNUM}
-ctibase 0x%08X" [expr 0xFC020000 + ($_i << 20)]]
+
+ # Create the target
+ eval [format "target create ${_TARGETNAME} aarch64 -endian $_ENDIAN
-dap ${_DAPNAME} -ap-num ${_APNUM} -cti ${_CTINAME} -coreid %d" $_i]
+ set _SMP_STR "${_SMP_STR} ${_TARGETNAME}"
+
+ # Clear CTI output/input enables that are not configured by OpenOCD for
aarch64
+ ${_TARGETNAME} configure -event examine-start [subst {
+ ${_CTINAME} write INEN0 0x00000000
+ ${_CTINAME} write INEN1 0x00000000
+ ${_CTINAME} write INEN2 0x00000000
+ ${_CTINAME} write INEN3 0x00000000
+ ${_CTINAME} write INEN4 0x00000000
+ ${_CTINAME} write INEN5 0x00000000
+ ${_CTINAME} write INEN6 0x00000000
+ ${_CTINAME} write INEN7 0x00000000
+ ${_CTINAME} write INEN8 0x00000000
+
+ ${_CTINAME} write OUTEN2 0x00000000
+ ${_CTINAME} write OUTEN3 0x00000000
+ ${_CTINAME} write OUTEN4 0x00000000
+ ${_CTINAME} write OUTEN5 0x00000000
+ ${_CTINAME} write OUTEN6 0x00000000
+ ${_CTINAME} write OUTEN7 0x00000000
+ ${_CTINAME} write OUTEN8 0x00000000
+ }]
+
+ # Enable OpenOCD HWTHREAD RTOS feature for GDB thread (CPU) selection
support
+ # This feature presents CPU cores ("hardware threads") in an SMP system
as threads to GDB
+ ${_TARGETNAME} configure -rtos hwthread
+}
+eval ${_SMP_STR}
--
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