This is an automated email from Gerrit. Jiri Kastner ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5879
-- gerrit commit d86217d6d9d588080d42cd37b7798b0fc4ce689a Author: Lubomir Rintel <[email protected]> Date: Mon Oct 19 00:55:32 2020 +0200 board: add Skytone Alpha 400 This adds the configuration for the MIPS subnotebook board that is known by many names -- Skytone Alpha 400 seems to be the OEM name. The unit I've tested this on was sold as "Elonex Onet+". Enough plafrom initialization is provided to make UART0 (routed to connector in battery compartment) and DRAM and access to NAND flash chip accesible. Change-Id: If21177ed7839e266bfd8f1fc397d4c04a3174dd1 Signed-off-by: Lubomir Rintel <[email protected]> Signed-off-by: Jiri Kastner <[email protected]> diff --git a/tcl/board/skytone_alpha400.cfg b/tcl/board/skytone_alpha400.cfg new file mode 100644 index 0000000..df8a349 --- /dev/null +++ b/tcl/board/skytone_alpha400.cfg @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Skytone Alpha 400 board (also known as Letux 400, Elonex Onet+, etc.) +# Copyright (C) 2020 Lubomir Rintel <[email protected]> + + +source [find target/jz4730.cfg] + +proc gpio_init { } { + global GPIO_BASE_ADDR + + # Enable UART0 pins + mww phys [expr $GPIO_BASE_ADDR + (0x14 + 3 * 0x30) ] 0x51555555 + + # Enable NAND flash pins of the EMC controller + mww phys [expr $GPIO_BASE_ADDR + (0x10 + 2 * 0x30) ] 0x64005400 + mww phys [expr $GPIO_BASE_ADDR + (0x14 + 2 * 0x30) ] 0x00004555 +} + +proc uart_init { } { + global UART0_DLLR + global UART0_DLHR + global UART0_IER + global UART0_FCR + global UART0_LCR + global UART0_SIRCR + + # Disable the UART + mww phys $UART0_IER 0x00000000 + mww phys $UART0_FCR 0x00000007 + + # UART mode, polarity, pulse width for 115200 bps + mww phys $UART0_SIRCR 0x0000001c + + # 115200 8n1 + mww phys $UART0_LCR 0x00000093 + mww phys $UART0_DLHR 0x00000000 + mww phys $UART0_DLLR 0x00000002 + mww phys $UART0_LCR 0x00000013 + + # Enable the UART with clear FIFO + mww phys $UART0_FCR 0x00000017 +} + +proc pll_init { } { + global CPM_CFCR + global CPM_PLCR1 + + # Create the 336M CPU clock from the 480M USB clock + mww phys $CPM_CFCR 0x0c422220 + + # PLL out + mww phys $CPM_PLCR1 0x5a000520 +} + +proc sdram_init { } { + global EMC_BCR + global EMC_DMCR + global EMC_RTCSR + global EMC_RTCNT + global EMC_RTCOR + global EMC_DMAR1 + global EMC_DMAR2 + global EMC_SDMR0 + global EMC_SDMR1 + + # Enable SPLIT + mww phys $EMC_BCR 0x00000002 + + # Ensure DRAM refresh disabled + mww phys $EMC_RTCSR 0x00000000 + mww phys $EMC_RTCOR 0x00000000 + mww phys $EMC_RTCNT 0x00000000 + + # 64MB per bank + mww phys $EMC_DMAR1 0x000020f4 + mww phys $EMC_DMAR2 0x000024f4 + + # Precharge + mww phys $EMC_DMCR 0x042a3211 + + # Configure DRAM refresh + mww phys $EMC_RTCOR 0x00000010 + mww phys $EMC_RTCSR 0x00000003 + + # Precharge both chips + mwb phys [expr $EMC_SDMR0 + 0x88 ] 0x00 + mwb phys [expr $EMC_SDMR1 + 0x88 ] 0x00 + + # Need upwards of 200us for precharge + sleep 1 + + # Enable refresh and set SDRAM mode + mww phys $EMC_DMCR 0x05aa3211 + + # Write SDRAM mode for both chips + mwb phys [expr $EMC_SDMR0 + 0x88 ] 0x00 + mwb phys [expr $EMC_SDMR1 + 0x88 ] 0x00 +} + +proc board_init { } { + gpio_init + uart_init + pll_init + sdram_init +} + +$_TARGETNAME configure -event reset-init { + board_init +} + +set _FLASHNAME $_CHIPNAME.flash +nand device $_FLASHNAME jz4730 $_TARGETNAME diff --git a/tcl/target/jz4730.cfg b/tcl/target/jz4730.cfg index bc47808..31df24b 100644 --- a/tcl/target/jz4730.cfg +++ b/tcl/target/jz4730.cfg @@ -1,9 +1,34 @@ # Ingenic JZ4730 (XBurst MIPS32r1-compatibe core) +set CPM_BASE_ADDR 0xb0000000 +set CPM_CFCR [expr $CPM_BASE_ADDR + 0x0000] +set CPM_PLCR1 [expr $CPM_BASE_ADDR + 0x0010] + set WDT_BASE_ADDR 0xb0004000 set WDT_WTCSR [expr $WDT_BASE_ADDR + 0x00] set WDT_WTCNT [expr $WDT_BASE_ADDR + 0x04] +set GPIO_BASE_ADDR 0xb0010000 + +set UART0_BASE_ADDR 0xb0030000 +set UART0_DLLR [expr $UART0_BASE_ADDR + 0x00] +set UART0_DLHR [expr $UART0_BASE_ADDR + 0x04] +set UART0_IER [expr $UART0_BASE_ADDR + 0x04] +set UART0_FCR [expr $UART0_BASE_ADDR + 0x08] +set UART0_LCR [expr $UART0_BASE_ADDR + 0x0c] +set UART0_SIRCR [expr $UART0_BASE_ADDR + 0x20] + +set EMC_BASE_ADDR 0xb3010000 +set EMC_BCR [expr $EMC_BASE_ADDR + 0x0000] +set EMC_DMCR [expr $EMC_BASE_ADDR + 0x0080] +set EMC_RTCSR [expr $EMC_BASE_ADDR + 0x0084] +set EMC_RTCNT [expr $EMC_BASE_ADDR + 0x0088] +set EMC_RTCOR [expr $EMC_BASE_ADDR + 0x008c] +set EMC_DMAR1 [expr $EMC_BASE_ADDR + 0x0090] +set EMC_DMAR2 [expr $EMC_BASE_ADDR + 0x0094] +set EMC_SDMR0 [expr $EMC_BASE_ADDR + 0xa000] +set EMC_SDMR1 [expr $EMC_BASE_ADDR + 0xb000] + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
