This is an automated email from Gerrit. Andreas Fritiofson ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5933
-- gerrit commit ac2e3f007f28db59916aa614f55583bfb71a5cf6 Author: Andreas Fritiofson <[email protected]> Date: Tue Nov 10 09:42:58 2020 +0100 [WIP] arm_adi_v5: Move DP init from SWD to ADI v5 layer Change-Id: I7d834e987c59e65084359b1005e67be3dda4ec94 Signed-off-by: Andreas Fritiofson <[email protected]> diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c index 71de222..f0bc856 100644 --- a/src/target/adi_v5_swd.c +++ b/src/target/adi_v5_swd.c @@ -81,16 +81,8 @@ static void swd_clear_sticky_errors(struct adiv5_dap *dap) static int swd_run_inner(struct adiv5_dap *dap) { const struct swd_driver *swd = adiv5_dap_swd_driver(dap); - int retval; - - retval = swd->run(); - - if (retval != ERROR_OK) { - /* fault response */ - dap->do_reconnect = true; - } - return retval; + return swd->run(); } static int swd_connect(struct adiv5_dap *dap) @@ -99,36 +91,12 @@ static int swd_connect(struct adiv5_dap *dap) uint32_t dpidr = 0xdeadbeef; int status; - /* FIXME validate transport config ... is the - * configured DAP present (check IDCODE)? - * Is *only* one DAP configured? - * - * MUST READ DPIDR - */ - - /* Check if we should reset srst already when connecting, but not if reconnecting. */ - if (!dap->do_reconnect) { - enum reset_types jtag_reset_config = jtag_get_reset_config(); - - if (jtag_reset_config & RESET_CNCT_UNDER_SRST) { - if (jtag_reset_config & RESET_SRST_NO_GATING) - adapter_assert_reset(); - else - LOG_WARNING("\'srst_nogate\' reset_config option is required"); - } - } - - int64_t timeout = timeval_ms() + 500; do { /* Note, debugport_init() does setup too */ swd->switch_seq(JTAG_TO_SWD); - /* Clear link state, including the SELECT cache. */ - dap->do_reconnect = false; - dap_invalidate_cache(dap); - status = swd_queue_dp_read(dap, DP_DPIDR, &dpidr); if (status == ERROR_OK) { status = swd_run_inner(dap); @@ -147,32 +115,10 @@ static int swd_connect(struct adiv5_dap *dap) LOG_INFO("SWD DPIDR %#8.8" PRIx32, dpidr); - do { - dap->do_reconnect = false; - - /* force clear all sticky faults */ - swd_clear_sticky_errors(dap); - - status = swd_run_inner(dap); - if (status != ERROR_WAIT) - break; - - alive_sleep(10); + /* force clear all sticky faults */ + swd_clear_sticky_errors(dap); - } while (timeval_ms() < timeout); - - if (status == ERROR_WAIT) { - LOG_WARNING("Connecting DP: staled AP operation, issuing ABORT"); - - dap->do_reconnect = false; - - swd->write_reg(swd_cmd(false, false, DP_ABORT), - DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0); - status = swd_run_inner(dap); - } - - if (status == ERROR_OK) - status = dap_dp_init(dap); + status = swd_run_inner(dap); return status; } @@ -190,14 +136,6 @@ static inline int check_sync(struct adiv5_dap *dap) return do_sync ? swd_run_inner(dap) : ERROR_OK; } -static int swd_check_reconnect(struct adiv5_dap *dap) -{ - if (dap->do_reconnect) - return swd_connect(dap); - - return ERROR_OK; -} - static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack) { const struct swd_driver *swd = adiv5_dap_swd_driver(dap); @@ -237,11 +175,7 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg, const struct swd_driver *swd = adiv5_dap_swd_driver(dap); assert(swd); - int retval = swd_check_reconnect(dap); - if (retval != ERROR_OK) - return retval; - - retval = swd_queue_dp_bankselect(dap, reg); + int retval = swd_queue_dp_bankselect(dap, reg); if (retval != ERROR_OK) return retval; @@ -254,12 +188,9 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg, uint32_t data) { const struct swd_driver *swd = adiv5_dap_swd_driver(dap); + int retval; assert(swd); - int retval = swd_check_reconnect(dap); - if (retval != ERROR_OK) - return retval; - swd_finish_read(dap); if (reg == DP_SELECT) { dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK); @@ -309,11 +240,7 @@ static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg, const struct swd_driver *swd = adiv5_dap_swd_driver(dap); assert(swd); - int retval = swd_check_reconnect(dap); - if (retval != ERROR_OK) - return retval; - - retval = swd_queue_ap_bankselect(ap, reg); + int retval = swd_queue_ap_bankselect(ap, reg); if (retval != ERROR_OK) return retval; @@ -330,12 +257,9 @@ static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg, const struct swd_driver *swd = adiv5_dap_swd_driver(dap); assert(swd); - int retval = swd_check_reconnect(dap); - if (retval != ERROR_OK) - return retval; swd_finish_read(dap); - retval = swd_queue_ap_bankselect(ap, reg); + int retval = swd_queue_ap_bankselect(ap, reg); if (retval != ERROR_OK) return retval; diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index a09e269..0a45f35 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -652,8 +652,22 @@ int dap_dp_init(struct adiv5_dap *dap) LOG_DEBUG("%s", adiv5_dap_name(dap)); + /* Check if we should reset srst already when connecting, but not if reconnecting. */ + if (!dap->do_reconnect) { + enum reset_types jtag_reset_config = jtag_get_reset_config(); + + if (jtag_reset_config & RESET_CNCT_UNDER_SRST) { + if (jtag_reset_config & RESET_SRST_NO_GATING) + adapter_assert_reset(); + else + LOG_WARNING("\'srst_nogate\' reset_config option is required"); + } + } + dap_invalidate_cache(dap); + dap->ops->connect(dap); + /* * Early initialize dap->dp_ctrl_stat. * In jtag mode only, if the following atomic reads fail and set the diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index ea71551..2b61a0c 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -357,6 +357,83 @@ enum ap_type { AP_TYPE_AHB5_AP = 0x5, /* AHB5 Memory-AP. */ }; +/* Queued MEM-AP memory mapped single word transfers. */ +int mem_ap_read_u32(struct adiv5_ap *ap, + uint32_t address, uint32_t *value); +int mem_ap_write_u32(struct adiv5_ap *ap, + uint32_t address, uint32_t value); + +/* Synchronous MEM-AP memory mapped single word transfers. */ +int mem_ap_read_atomic_u32(struct adiv5_ap *ap, + uint32_t address, uint32_t *value); +int mem_ap_write_atomic_u32(struct adiv5_ap *ap, + uint32_t address, uint32_t value); + +/* Synchronous MEM-AP memory mapped bus block transfers. */ +int mem_ap_read_buf(struct adiv5_ap *ap, + uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); +int mem_ap_write_buf(struct adiv5_ap *ap, + const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); + +/* Synchronous, non-incrementing buffer functions for accessing fifos. */ +int mem_ap_read_buf_noincr(struct adiv5_ap *ap, + uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); +int mem_ap_write_buf_noincr(struct adiv5_ap *ap, + const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); + +/* Initialisation of the debug system, power domains and registers */ +int dap_dp_init(struct adiv5_dap *dap); +int mem_ap_init(struct adiv5_ap *ap); + +/* Invalidate cached DP select and cached TAR and CSW of all APs */ +void dap_invalidate_cache(struct adiv5_dap *dap); + +/* Probe the AP for ROM Table location */ +int dap_get_debugbase(struct adiv5_ap *ap, + uint32_t *dbgbase, uint32_t *apid); + +/* Probe Access Ports to find a particular type */ +int dap_find_ap(struct adiv5_dap *dap, + enum ap_type type_to_find, + struct adiv5_ap **ap_out); + +static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num) +{ + return &dap->ap[ap_num]; +} + +/* Lookup CoreSight component */ +int dap_lookup_cs_component(struct adiv5_ap *ap, + uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx); + +struct target; + +/* Put debug link into SWD mode */ +int dap_to_swd(struct adiv5_dap *dap); + +/* Put debug link into JTAG mode */ +int dap_to_jtag(struct adiv5_dap *dap); + +extern const struct command_registration dap_instance_commands[]; + +struct arm_dap_object; +extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o); +extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj); +extern int dap_info_command(struct command_invocation *cmd, + struct adiv5_ap *ap); +extern int dap_register_commands(struct command_context *cmd_ctx); +extern const char *adiv5_dap_name(struct adiv5_dap *self); +extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self); +extern int dap_cleanup_all(void); + +struct adiv5_private_config { + int ap_num; + struct adiv5_dap *dap; +}; + +extern int adiv5_verify_config(struct adiv5_private_config *pc); +extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi); + /** * Send an adi-v5 sequence to the DAP. * @@ -372,6 +449,23 @@ static inline int dap_send_sequence(struct adiv5_dap *dap, return dap->ops->send_sequence(dap, seq); } +static int dap_check_reconnect(struct adiv5_dap *dap) +{ + int retval = ERROR_OK; + if (dap->do_reconnect) { + retval = dap->ops->connect(dap); + if (retval != ERROR_OK) { + return retval; + } + retval = dap_dp_init(dap); + if (retval != ERROR_OK) { + return retval; + } + dap->do_reconnect = false; + } + return retval; +} + /** * Queue a DP register read. * Note that not all DP registers are readable; also, that JTAG and SWD @@ -388,6 +482,9 @@ static inline int dap_queue_dp_read(struct adiv5_dap *dap, unsigned reg, uint32_t *data) { assert(dap->ops != NULL); + int retval = dap_check_reconnect(dap); + if (retval != ERROR_OK) + return retval; return dap->ops->queue_dp_read(dap, reg, data); } @@ -406,6 +503,9 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap, unsigned reg, uint32_t data) { assert(dap->ops != NULL); + int retval = dap_check_reconnect(dap); + if (retval != ERROR_OK) + return retval; return dap->ops->queue_dp_write(dap, reg, data); } @@ -423,6 +523,9 @@ static inline int dap_queue_ap_read(struct adiv5_ap *ap, unsigned reg, uint32_t *data) { assert(ap->dap->ops != NULL); + int retval = dap_check_reconnect(ap->dap); + if (retval != ERROR_OK) + return retval; return ap->dap->ops->queue_ap_read(ap, reg, data); } @@ -439,6 +542,9 @@ static inline int dap_queue_ap_write(struct adiv5_ap *ap, unsigned reg, uint32_t data) { assert(ap->dap->ops != NULL); + int retval = dap_check_reconnect(ap->dap); + if (retval != ERROR_OK) + return retval; return ap->dap->ops->queue_ap_write(ap, reg, data); } @@ -524,81 +630,4 @@ static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg, } } -/* Queued MEM-AP memory mapped single word transfers. */ -int mem_ap_read_u32(struct adiv5_ap *ap, - uint32_t address, uint32_t *value); -int mem_ap_write_u32(struct adiv5_ap *ap, - uint32_t address, uint32_t value); - -/* Synchronous MEM-AP memory mapped single word transfers. */ -int mem_ap_read_atomic_u32(struct adiv5_ap *ap, - uint32_t address, uint32_t *value); -int mem_ap_write_atomic_u32(struct adiv5_ap *ap, - uint32_t address, uint32_t value); - -/* Synchronous MEM-AP memory mapped bus block transfers. */ -int mem_ap_read_buf(struct adiv5_ap *ap, - uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); -int mem_ap_write_buf(struct adiv5_ap *ap, - const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); - -/* Synchronous, non-incrementing buffer functions for accessing fifos. */ -int mem_ap_read_buf_noincr(struct adiv5_ap *ap, - uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); -int mem_ap_write_buf_noincr(struct adiv5_ap *ap, - const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); - -/* Initialisation of the debug system, power domains and registers */ -int dap_dp_init(struct adiv5_dap *dap); -int mem_ap_init(struct adiv5_ap *ap); - -/* Invalidate cached DP select and cached TAR and CSW of all APs */ -void dap_invalidate_cache(struct adiv5_dap *dap); - -/* Probe the AP for ROM Table location */ -int dap_get_debugbase(struct adiv5_ap *ap, - uint32_t *dbgbase, uint32_t *apid); - -/* Probe Access Ports to find a particular type */ -int dap_find_ap(struct adiv5_dap *dap, - enum ap_type type_to_find, - struct adiv5_ap **ap_out); - -static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num) -{ - return &dap->ap[ap_num]; -} - -/* Lookup CoreSight component */ -int dap_lookup_cs_component(struct adiv5_ap *ap, - uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx); - -struct target; - -/* Put debug link into SWD mode */ -int dap_to_swd(struct adiv5_dap *dap); - -/* Put debug link into JTAG mode */ -int dap_to_jtag(struct adiv5_dap *dap); - -extern const struct command_registration dap_instance_commands[]; - -struct arm_dap_object; -extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o); -extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj); -extern int dap_info_command(struct command_invocation *cmd, - struct adiv5_ap *ap); -extern int dap_register_commands(struct command_context *cmd_ctx); -extern const char *adiv5_dap_name(struct adiv5_dap *self); -extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self); -extern int dap_cleanup_all(void); - -struct adiv5_private_config { - int ap_num; - struct adiv5_dap *dap; -}; - -extern int adiv5_verify_config(struct adiv5_private_config *pc); -extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi); - #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */ diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c index 56442f1..220278b 100644 --- a/src/target/arm_dap.c +++ b/src/target/arm_dap.c @@ -126,7 +126,7 @@ static int dap_init_all(void) } else dap->ops = &jtag_dp_ops; - retval = dap->ops->connect(dap); + retval = dap_dp_init(dap); if (retval != ERROR_OK) return retval; } -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
