This is an automated email from Gerrit.
Adrian M Negreanu (adrian.negre...@nxp.com) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/6043
-- gerrit
commit f6687c515c257d30f4ed59b70b9a04f94bd69a48
Author: Adrian Negreanu <adrian.negre...@nxp.com>
Date: Fri Nov 20 18:53:51 2020 +0200
armv7m_trace_itm_config: wait for ITMBusy to be cleared
pg315 of CoreSight Components:
It is recommended that the ITMEn bit is cleared and waits for the
ITMBusy bit to be cleared, before changing any fields in the
Control Register, otherwise the behavior can be unpredictable.
Change-Id: Ie9a2b842825c98ee5edc9a35776320c668047769
Signed-off-by: Adrian Negreanu <adrian.negre...@nxp.com>
diff --git a/src/target/armv7m_trace.c b/src/target/armv7m_trace.c
index b6f915d..ba57853 100644
--- a/src/target/armv7m_trace.c
+++ b/src/target/armv7m_trace.c
@@ -162,6 +162,31 @@ int armv7m_trace_itm_config(struct target *target)
if (retval != ERROR_OK)
return retval;
+ /* pg315 of CoreSight Components
+ * It is recommended that the ITMEn bit is cleared and waits for the
+ * ITMBusy bit to be cleared, before changing any fields in the
+ * Control Register, otherwise the behavior can be unpredictable.
+ */
+#define ITM_TCR_ITMENA_BIT 0
+#define ITM_TCR_BUSY_BIT 23
+ uint32_t itm_tcr;
+ retval = target_read_u32(target, ITM_TCR, &itm_tcr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target,
+ ITM_TCR,
+ itm_tcr & ~(1<<ITM_TCR_ITMENA_BIT)
+ );
+ if (retval != ERROR_OK)
+ return retval;
+
+ do {
+ retval = target_read_u32(target, ITM_TCR, &itm_tcr);
+ if (retval != ERROR_OK)
+ return retval;
+ printf("wai\n");
+ } while (itm_tcr&ITM_TCR_BUSY_BIT);
+
/* Enable ITM, TXENA, set TraceBusID and other parameters */
retval = target_write_u32(target, ITM_TCR, (1 << 0) | (1 << 3) |
(trace_config->itm_diff_timestamps << 1) |
--
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