This is an automated email from Gerrit. Ioannis Glaropoulos ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/6093
-- gerrit commit 350d3efdd8b51a7bbaa1728780d4d09690a3842f Author: Ioannis Glaropoulos <[email protected]> Date: Tue Mar 9 13:29:12 2021 +0100 cortex_m: clear halt debug enable bit in cortex_m_deinit_target Before exiting cortex_m_deinit_target(), write to DHCSR to clear the DHCSR control bits (primarily DHCSR.DEBUGEN), to disable the halt debug mode. This is required for the target to be in normal (i.e. not debug) mode after the session shuts down. The reason for this is that DHCSR.DEBUGEN can only be cleared by DAP (not software) or after a power-on reset. Change-Id: I90c5f7ca085c9e1a211b0a4dc0e0ff6f0a54889d Signed-off-by: Ioannis Glaropoulos <[email protected]> diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index ce2c426..34a3e9b 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -237,6 +237,17 @@ static int cortex_m_clear_halt(struct target *target) return ERROR_OK; } +static int cortex_m_clear_debug_halt_enable(struct target *target) +{ + struct cortex_m_common *cortex_m = target_to_cm(target); + struct armv7m_common *armv7m = &cortex_m->armv7m; + + /* Exit debug state by clearing the Halt Debug Enable bit in DHCSR */ + cortex_m->dcb_dhcsr = DBGKEY; + + return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr); +} + static int cortex_m_single_step_core(struct target *target) { struct cortex_m_common *cortex_m = target_to_cm(target); @@ -1653,6 +1664,7 @@ void cortex_m_deinit_target(struct target *target) free(cortex_m->fp_comparator_list); cortex_m_dwt_free(target); + cortex_m_clear_debug_halt_enable(target); armv7m_free_reg_cache(target); free(target->private_config); -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
