Hi Tim, I'm wondering why the registers for RISC-V targets are invalid (register cache) after halting the core. When I try to display the values for all registers with "reg" I get the following output:
> reg ===== RISC-V Registers (0) zero (/32) (1) ra (/32) (2) sp (/32) (3) gp (/32) (4) tp (/32) (5) t0 (/32) (6) t1 (/32) (7) t2 (/32) (8) fp (/32) (9) s1 (/32) (10) a0 (/32) (11) a1 (/32) (12) a2 (/32) (13) a3 (/32) (14) a4 (/32) (15) a5 (/32) (16) a6 (/32) (17) a7 (/32) (18) s2 (/32) (19) s3 (/32) (20) s4 (/32) (21) s5 (/32) (22) s6 (/32) (23) s7 (/32) (24) s8 (/32) (25) s9 (/32) (26) s10 (/32) (27) s11 (/32) (28) t3 (/32) (29) t4 (/32) (30) t5 (/32) (31) t6 (/32) (32) pc (/32) ... The OpenOCD riscv fork behaves the same. Is there a good reason for that? Best regards, Marc
