This is an automated email from Gerrit. Tarek BOCHKATI ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/6437
-- gerrit commit 280705f49a037f5394ccb613a2f2d56ec1a76fd1 Author: Tarek BOCHKATI <[email protected]> Date: Sat Aug 14 14:31:17 2021 +0100 flash/stm32l4x: avoid using magic numbers [WIP] rework DBANK bits in probe function Change-Id: I54c41f31c16b91904e8cbca823b90caa3807826d Signed-off-by: Tarek BOCHKATI <[email protected]> diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c index 66e6cdb..bd21ab1 100644 --- a/src/flash/nor/stm32l4x.c +++ b/src/flash/nor/stm32l4x.c @@ -357,7 +357,7 @@ static const struct stm32l4_rev stm32_497_revs[] = { static const struct stm32l4_part_info stm32l4_parts[] = { { - .id = 0x415, + .id = DEVID_STM32L47_L48xx, .revs = stm32_415_revs, .num_revs = ARRAY_SIZE(stm32_415_revs), .device_str = "STM32L47/L48xx", @@ -369,7 +369,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x435, + .id = DEVID_STM32L43_L44xx, .revs = stm32_435_revs, .num_revs = ARRAY_SIZE(stm32_435_revs), .device_str = "STM32L43/L44xx", @@ -381,7 +381,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x456, + .id = DEVID_STM32G05_G06xx, .revs = stm32_456_revs, .num_revs = ARRAY_SIZE(stm32_456_revs), .device_str = "STM32G05/G06xx", @@ -393,7 +393,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x460, + .id = DEVID_STM32G07_G08xx, .revs = stm32_460_revs, .num_revs = ARRAY_SIZE(stm32_460_revs), .device_str = "STM32G07/G08xx", @@ -405,7 +405,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x461, + .id = DEVID_STM32L49_L4Axx, .revs = stm32_461_revs, .num_revs = ARRAY_SIZE(stm32_461_revs), .device_str = "STM32L49/L4Axx", @@ -417,7 +417,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x462, + .id = DEVID_STM32L45_L46xx, .revs = stm32_462_revs, .num_revs = ARRAY_SIZE(stm32_462_revs), .device_str = "STM32L45/L46xx", @@ -429,7 +429,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x464, + .id = DEVID_STM32L41_L42xx, .revs = stm32_464_revs, .num_revs = ARRAY_SIZE(stm32_464_revs), .device_str = "STM32L41/L42xx", @@ -441,10 +441,10 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x466, + .id = DEVID_STM32G03_G04xx, .revs = stm32_466_revs, .num_revs = ARRAY_SIZE(stm32_466_revs), - .device_str = "STM32G03/G04xx", + .device_str = "STM32G03x/G04xx", .max_flash_size_kb = 64, .flags = F_NONE, .flash_regs_base = 0x40022000, @@ -453,10 +453,10 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x467, + .id = DEVID_STM32G0B_G0Cxx, .revs = stm32_467_revs, .num_revs = ARRAY_SIZE(stm32_467_revs), - .device_str = "STM32G0Bx/G0Cx", + .device_str = "STM32G0B/G0Cx", .max_flash_size_kb = 512, .flags = F_HAS_DUAL_BANK, .flash_regs_base = 0x40022000, @@ -465,7 +465,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x468, + .id = DEVID_STM32G43_G44xx, .revs = stm32_468_revs, .num_revs = ARRAY_SIZE(stm32_468_revs), .device_str = "STM32G43/G44xx", @@ -477,7 +477,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x469, + .id = DEVID_STM32G47_G48xx, .revs = stm32_469_revs, .num_revs = ARRAY_SIZE(stm32_469_revs), .device_str = "STM32G47/G48xx", @@ -489,7 +489,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x470, + .id = DEVID_STM32L4R_L4Sxx, .revs = stm32_470_revs, .num_revs = ARRAY_SIZE(stm32_470_revs), .device_str = "STM32L4R/L4Sxx", @@ -501,10 +501,10 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x471, + .id = DEVID_STM32L4P_L4Qxx, .revs = stm32_471_revs, .num_revs = ARRAY_SIZE(stm32_471_revs), - .device_str = "STM32L4P5/L4Q5x", + .device_str = "STM32L4P/L4Qxx", .max_flash_size_kb = 1024, .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX, .flash_regs_base = 0x40022000, @@ -513,7 +513,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x472, + .id = DEVID_STM32L55_L56xx, .revs = stm32_472_revs, .num_revs = ARRAY_SIZE(stm32_472_revs), .device_str = "STM32L55/L56xx", @@ -525,7 +525,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 512, }, { - .id = 0x479, + .id = DEVID_STM32G49_G4Axx, .revs = stm32_479_revs, .num_revs = ARRAY_SIZE(stm32_479_revs), .device_str = "STM32G49/G4Axx", @@ -537,7 +537,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x482, + .id = DEVID_STM32U57_U58xx, .revs = stm32_482_revs, .num_revs = ARRAY_SIZE(stm32_482_revs), .device_str = "STM32U57/U58xx", @@ -549,7 +549,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 512, }, { - .id = 0x494, + .id = DEVID_STM32WB1x, .revs = stm32_494_revs, .num_revs = ARRAY_SIZE(stm32_494_revs), .device_str = "STM32WB1x", @@ -561,7 +561,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x495, + .id = DEVID_STM32WB5x, .revs = stm32_495_revs, .num_revs = ARRAY_SIZE(stm32_495_revs), .device_str = "STM32WB5x", @@ -573,7 +573,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x496, + .id = DEVID_STM32WB3x, .revs = stm32_496_revs, .num_revs = ARRAY_SIZE(stm32_496_revs), .device_str = "STM32WB3x", @@ -585,10 +585,10 @@ static const struct stm32l4_part_info stm32l4_parts[] = { .otp_size = 1024, }, { - .id = 0x497, + .id = DEVID_STM32WLE_WL5xx, .revs = stm32_497_revs, .num_revs = ARRAY_SIZE(stm32_497_revs), - .device_str = "STM32WLEx/WL5x", + .device_str = "STM32WLE/WL5x", .max_flash_size_kb = 256, .flags = F_NONE, .flash_regs_base = 0x58004000, @@ -1798,11 +1798,11 @@ static int stm32l4_probe(struct flash_bank *bank) bool use_dbank_bit = false; switch (device_id) { - case 0x415: /* STM32L47/L48xx */ - case 0x461: /* STM32L49/L4Axx */ + case DEVID_STM32L47_L48xx: + case DEVID_STM32L49_L4Axx: /* if flash size is max (1M) the device is always dual bank - * 0x415: has variants with 512K - * 0x461: has variants with 512 and 256 + * STM32L47/L48xx: has variants with 512K + * STM32L49/L4Axx: has variants with 512 and 256 * for these variants: * if DUAL_BANK = 0 -> single bank * else -> dual bank without gap @@ -1818,21 +1818,21 @@ static int stm32l4_probe(struct flash_bank *bank) stm32l4_info->bank1_sectors = num_pages / 2; } break; - case 0x435: /* STM32L43/L44xx */ - case 0x456: /* STM32G05/G06xx */ - case 0x460: /* STM32G07/G08xx */ - case 0x462: /* STM32L45/L46xx */ - case 0x464: /* STM32L41/L42xx */ - case 0x466: /* STM32G03/G04xx */ - case 0x468: /* STM32G43/G44xx */ - case 0x479: /* STM32G49/G4Axx */ - case 0x494: /* STM32WB1x */ + case DEVID_STM32L43_L44xx: + case DEVID_STM32G05_G06xx: + case DEVID_STM32G07_G08xx: + case DEVID_STM32L45_L46xx: + case DEVID_STM32L41_L42xx: + case DEVID_STM32G03_G04xx: + case DEVID_STM32G43_G44xx: + case DEVID_STM32G49_G4Axx: + case DEVID_STM32WB1x: /* single bank flash */ page_size_kb = 2; num_pages = flash_size_kb / page_size_kb; stm32l4_info->bank1_sectors = num_pages; break; - case 0x467: /* STM32G0B/G0Cxx */ + case DEVID_STM32G0B_G0Cxx: /* single/dual bank depending on bit(21) */ page_size_kb = 2; num_pages = flash_size_kb / page_size_kb; @@ -1846,7 +1846,7 @@ static int stm32l4_probe(struct flash_bank *bank) stm32l4_info->bank1_sectors = num_pages / 2; } break; - case 0x469: /* STM32G47/G48xx */ + case DEVID_STM32G47_G48xx: /* STM32G47/8 can be single/dual bank: * if DUAL_BANK = 0 -> single bank * else -> dual bank WITH gap @@ -1865,8 +1865,8 @@ static int stm32l4_probe(struct flash_bank *bank) (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb); } break; - case 0x470: /* STM32L4R/L4Sxx */ - case 0x471: /* STM32L4P5/L4Q5x */ + case DEVID_STM32L4R_L4Sxx: + case DEVID_STM32L4P_L4Qxx: /* STM32L4R/S can be single/dual bank: * if size = 2M check DBANK bit(22) * if size = 1M check DB1M bit(21) @@ -1886,7 +1886,7 @@ static int stm32l4_probe(struct flash_bank *bank) stm32l4_info->bank1_sectors = num_pages / 2; } break; - case 0x472: /* STM32L55/L56xx */ + case DEVID_STM32L55_L56xx: /* STM32L55/L56xx can be single/dual bank: * if size = 512K check DBANK bit(22) * if size = 256K check DB256K bit(21) @@ -1903,7 +1903,7 @@ static int stm32l4_probe(struct flash_bank *bank) stm32l4_info->bank1_sectors = num_pages / 2; } break; - case 0x482: /* STM32U57/U58xx */ + case DEVID_STM32U57_U58xx: /* if flash size is max (2M) the device is always dual bank * otherwise check DUALBANK bit(21) */ @@ -1915,14 +1915,14 @@ static int stm32l4_probe(struct flash_bank *bank) stm32l4_info->bank1_sectors = num_pages / 2; } break; - case 0x495: /* STM32WB5x */ - case 0x496: /* STM32WB3x */ + case DEVID_STM32WB5x: + case DEVID_STM32WB3x: /* single bank flash */ page_size_kb = 4; num_pages = flash_size_kb / page_size_kb; stm32l4_info->bank1_sectors = num_pages; break; - case 0x497: /* STM32WLEx/WL5x */ + case DEVID_STM32WLE_WL5xx: /* single bank flash */ page_size_kb = 2; num_pages = flash_size_kb / page_size_kb; diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h index a3067c0..0e79286 100644 --- a/src/flash/nor/stm32l4x.h +++ b/src/flash/nor/stm32l4x.h @@ -69,11 +69,33 @@ #define FLASH_SECBB_SECURE 0xFFFFFFFF #define FLASH_SECBB_NON_SECURE 0 -/* other registers */ +/* IDCODE register possible addresses */ #define DBGMCU_IDCODE_G0 0x40015800 #define DBGMCU_IDCODE_L4_G4 0xE0042000 #define DBGMCU_IDCODE_L5 0xE0044000 +/* Supported device IDs */ +#define DEVID_STM32L47_L48xx 0x415 +#define DEVID_STM32L43_L44xx 0x435 +#define DEVID_STM32G05_G06xx 0x456 +#define DEVID_STM32G07_G08xx 0x460 +#define DEVID_STM32L49_L4Axx 0x461 +#define DEVID_STM32L45_L46xx 0x462 +#define DEVID_STM32L41_L42xx 0x464 +#define DEVID_STM32G03_G04xx 0x466 +#define DEVID_STM32G0B_G0Cxx 0x467 +#define DEVID_STM32G43_G44xx 0x468 +#define DEVID_STM32G47_G48xx 0x469 +#define DEVID_STM32L4R_L4Sxx 0x470 +#define DEVID_STM32L4P_L4Qxx 0x471 +#define DEVID_STM32L55_L56xx 0x472 +#define DEVID_STM32G49_G4Axx 0x479 +#define DEVID_STM32U57_U58xx 0x482 +#define DEVID_STM32WB1x 0x494 +#define DEVID_STM32WB5x 0x495 +#define DEVID_STM32WB3x 0x496 +#define DEVID_STM32WLE_WL5xx 0x497 + #define STM32_FLASH_BANK_BASE 0x08000000 #define STM32_FLASH_S_BANK_BASE 0x0C000000 --
