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"Adrien Grassein <adrien.grass...@gmail.com>" just uploaded a new patch set to
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-- gerrit
commit 3f094cda8c14a3dbdcb155bc9c9bbc3c8b37be71
Author: Adrien Grassein <adrien.grass...@gmail.com>
Date: Fri Dec 17 13:47:08 2021 +0100
tcl: lpc55S69: add target config file
The lpc55S69 features two m33 cores.
Signed-off-by: Adrien Grassein <adrien.grass...@gmail.com>
Change-Id: I039023bcaa36a696990546b28e34bf1ad42f649a
diff --git a/tcl/target/lpc55S69.cfg b/tcl/target/lpc55S69.cfg
new file mode 100644
index 000000000..2f500f7b8
--- /dev/null
+++ b/tcl/target/lpc55S69.cfg
@@ -0,0 +1,25 @@
+#lpc55SS9 is an NXP microcontroller with two m33 cores.
+source [find target/swj-dp.tcl]
+
+adapter speed 500
+
+set _CHIPNAME lpc55S69
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0x6ba02477
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_CHIPNAME.CORE0 cortex_m -dap $_CHIPNAME.dap -ap-num 0 -coreid 0
+$_CHIPNAME.CORE0 cortex_m reset_config sysresetreq
+
+# lpc55S69 not follow the ARM procedure to halt the processor after a reset.
+# We need to place a watchpoint at 0x50000040.
+# This procedure is explained in the chapter
+# "51.6.4 Halting execution immediately following ROM execution" of the
+# UM11126 LPC55S6x/LPC55S2x/LPC552x User manual rev 2.4 document.
+# Here we use the very first comparator of the m33.
+$_CHIPNAME.CORE0 configure -event reset-assert-pre {
+ mww 0xE0001028 0
+ mww 0xE0001020 0x50000040
+ mww 0xE0001028 2068
+}
+
--
