This is an automated email from Gerrit.
"Maximilian Gerhardt <maximilian.gerha...@rub.de>" just uploaded a new patch
set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/6794
-- gerrit
commit 49f69a73734bff7cbe9fb889951c15ff5a413a7e
Author: Max Gerhardt <maximilian.gerha...@rub.de>
Date: Sun Dec 26 13:03:22 2021 +0100
Add GD32E50x Support
See user manual at
https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32E50x/GD32E50x_User_Manual_Rev1.2.pdf
for reference.
Notes / change justication:
* used hardware: GD32E503C-START board with GD32E503CET6 chip and on-board
CMSIS-DAP ("GD-Link") probe
* SWD DPIDR: 0x0be12477
* DBGMCU ID code: 0x20030444
* device id part 0x444 overlaps with existing stm32f03x, had to add check
on revision ID of my particular chip (0x2003) to avoid confusion, not too nice
* device_id_register = 0xE0044000 is correct per page 270
* flash_size_reg = 0x1FFFF7E0 is correct per page 44
* page_size = 8192, ppage_size = 1 correct per page 47 and 57
* user_data_offset = 2 (bits), option_offset = 10 (bits) hopefully correct
per page 63
* gd32e50x.cfg's DBG_CTL address and content correct per page 270
* flashing of binaries and opening of a GDB server works (blinky example
tested)
* "flash info 0" shows expected protected page layout
Remaining bugs:
* after core is halted ("halt" command), MCU seems to reset continously,
but always after a different delay (between 5 seconds and 2 minutes). error
messages: "error writing data: (null), Polling target gd32e50x.cpu failed,
trying to reexamine, SWD DPIDR 0x0be12477, gd32e50x.cpu: Cortex-M33 r0p4
processor detected, gd32e50x.cpu: target has 8 breakpoints, 4 watchpoints"
* looks like watchdog reset, but examination of DBG_CTL register via "mrw
0xE0044004" shows all relevant bits are on -- no idea what's happening here
* tests done with Linux guest VM (VirtualBox) inside Windows host and USB
forwarding, did not test on Windows host itslef
Related ticket: https://sourceforge.net/p/openocd/tickets/328/
Signed-off-by: Max Gerhardt <maximilian.gerha...@rub.de>
Change-Id: I4ab4eb7a6514c2e1c6ce4333bed1ab5ffecb5cee
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 90cee6412..b10504601 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -643,6 +643,9 @@ static int stm32x_get_device_id(struct flash_bank *bank,
uint32_t *device_id)
case CORTEX_M23_PARTNO: /* GD32E23x devices */
device_id_register = 0x40015800;
break;
+ case CORTEX_M33_PARTNO: /* GD32E50x devices */
+ device_id_register = 0xE0044000;
+ break;
default:
LOG_ERROR("Cannot identify target as a stm32x");
return ERROR_FAIL;
@@ -680,6 +683,9 @@ static int stm32x_get_flash_size(struct flash_bank *bank,
uint16_t *flash_size_i
case CORTEX_M23_PARTNO: /* GD32E23x devices */
flash_size_reg = 0x1FFFF7E0;
break;
+ case CORTEX_M33_PARTNO: /* GD32E50x devices */
+ flash_size_reg = 0x1FFFF7E0;
+ break;
default:
LOG_ERROR("Cannot identify target as a stm32x");
return ERROR_FAIL;
@@ -730,15 +736,26 @@ static int stm32x_probe(struct flash_bank *bank)
stm32x_info->default_rdp = 0xAA;
stm32x_info->can_load_options = true;
break;
- case 0x444: /* stm32f03x */
+ case 0x444: /* stm32f03x, gd32e50x */
case 0x445: /* stm32f04x */
- page_size = 1024;
- stm32x_info->ppage_size = 4;
- max_flash_size_in_kb = 32;
- stm32x_info->user_data_offset = 16;
- stm32x_info->option_offset = 6;
- stm32x_info->default_rdp = 0xAA;
- stm32x_info->can_load_options = true;
+ /* explicitly for our gd32e503 case */
+ if (device_id == 0x444 && rev_id == 0x2003) {
+ page_size = 8192; /* flash page size is 8Kbyte */
+ stm32x_info->ppage_size = 1; /* 1 page per protection
block, except for pages 31-63 */
+ max_flash_size_in_kb = 512;
+ stm32x_info->user_data_offset = 2; //to the right of
user_data there are only 2 bits (SPC, OBERR)
+ stm32x_info->option_offset = 10; //to the right of
DATA, the are 10 bits.
+ break;
+ } else {
+ /* stm32f03x, stm32f04x */
+ page_size = 1024;
+ stm32x_info->ppage_size = 4;
+ max_flash_size_in_kb = 32;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0xAA;
+ stm32x_info->can_load_options = true;
+ }
break;
case 0x448: /* stm32f07x */
page_size = 2048;
@@ -1154,8 +1171,13 @@ static int get_stm32x_info(struct flash_bank *bank,
struct command_invocation *c
break;
case 0x444:
- device_str = "STM32F03x";
- rev_str = get_stm32f0_revision(rev_id);
+ /* GD32E50x */
+ if (rev_id == 0x2003) {
+ device_str = "GD32E50x";
+ } else {
+ device_str = "STM32F03x";
+ rev_str = get_stm32f0_revision(rev_id);
+ }
break;
case 0x440:
diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
index 16cbe1950..7bd0c2237 100644
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -122,5 +122,6 @@ proc stm32u5x args { eval stm32l4x $args }
proc stm32wbx args { eval stm32l4x $args }
proc stm32wlx args { eval stm32l4x $args }
-# gd32e23x uses the same flash driver as the stm32f1x
+# gd32e23x and gd32e50x use the same flash driver as the stm32f1x
proc gd32e23x args { eval stm32f1x $args }
+proc gd32e50x args { eval stm32f1x $args }
diff --git a/tcl/target/gd32e50x.cfg b/tcl/target/gd32e50x.cfg
new file mode 100644
index 000000000..0e5e57d24
--- /dev/null
+++ b/tcl/target/gd32e50x.cfg
@@ -0,0 +1,75 @@
+
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for GigaDevice gd32e50x Cortex-M33 Series
+
+# https://www.gigadevice.com/microcontroller/gd32e503cet6/
+
+#
+# gd32e50x devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME gd32e50x
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 50K. Every GD32E50x has at least 80K SRAM.
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0xc800
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+ set _FLASH_SIZE $FLASH_SIZE
+} else {
+ # autodetect size
+ set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # this is the SW-DP tap id not the jtag tap id
+ set _CPUTAPID 0x0be12477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# SWD speed (may be updated to higher value in board config file)
+adapter speed 1000
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+ # Debug clock enable
+ # RCU_APB2EN |= DBGMCUEN
+ mmw 0x40021018 0x00400000 0
+
+ # Stop watchdog counters during halt
+ # DBG_CTL |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD
+ mmw 0xE0044004 0x00000307 0
+}
\ No newline at end of file
--
