This is an automated email from Gerrit.
"Maximilian Gerhardt <maximilian.gerha...@rub.de>" just uploaded a new patch
set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/6795
-- gerrit
commit 6af9f57d2608a69dc2f358653d8b39d59df7b998
Author: Max Gerhardt <maximilian.gerha...@rub.de>
Date: Mon Dec 27 23:01:59 2021 +0100
flash/stm32f1x: Add GD32E50x Support
See user manual at
https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32E50x/GD32E50x_User_Manual_Rev1.2.pdf
for reference.
Notes / change justication:
* used hardware: GD32E503C-START board with GD32E503CET6 chip and on-board
CMSIS-DAP ("GD-Link") probe
* SWD DPIDR: 0x0be12477
* DBGMCU ID code: 0x20030444
* device id part 0x444 overlaps with existing stm32f03x, had to add check
on revision ID of my particular chip (0x2003) to avoid confusion, not too nice
* device_id_register = 0xE0044000 is correct per page 270
* flash_size_reg = 0x1FFFF7E0 is correct per page 44
* page_size = 8192, ppage_size = 1 correct per page 47 and 57
* for user_data_offset = 10 (bits), option_offset = 0 (bits), see page 63,
same as for GD32F103
* gd32e50x.cfg's DBG_CTL address and content correct per page 270
* flashing of binaries and opening of a GDB server works (blinky example
tested)
* "flash info 0" shows expected protected page layout
Remaining topics:
* When testing in a VM, the error message "error writing data: (null),
Polling target gd32e50x.cpu failed, trying to reexamine" occured, testing
outside a VM is an outstanding task..
* the "if (device_id == 0x444 && rev_id == 0x2003)" check might not get all
E50x devices, only tested for one particular GD32E503CE chip.
Related ticket: https://sourceforge.net/p/openocd/tickets/328/
Signed-off-by: Max Gerhardt <maximilian.gerha...@rub.de>
Change-Id: I0e6044e7b6eb96058263919dab86e3877e48f546
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 456944a6c..6ad58a92e 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -743,9 +743,8 @@ static int stm32x_probe(struct flash_bank *bank)
page_size = 8192; /* flash page size is 8Kbyte */
stm32x_info->ppage_size = 1; /* 1 page per protection
block, except for pages 31-63 */
max_flash_size_in_kb = 512;
- stm32x_info->user_data_offset = 2; /* to the right of
user_data there are only 2 bits (SPC, OBERR) */
- stm32x_info->option_offset = 10; /* to the right of
DATA, the are 10 bits */
- break;
+ stm32x_info->user_data_offset = 10; /* same as in
GD32F103 */
+ stm32x_info->option_offset = 0;
} else {
/* stm32f03x, stm32f04x */
page_size = 1024;
diff --git a/tcl/target/gd32e50x.cfg b/tcl/target/gd32e50x.cfg
index 0e5e57d24..1c82e3a4b 100644
--- a/tcl/target/gd32e50x.cfg
+++ b/tcl/target/gd32e50x.cfg
@@ -6,7 +6,7 @@
# https://www.gigadevice.com/microcontroller/gd32e503cet6/
#
-# gd32e50x devices support SWD transports only.
+# gd32e50x devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
@@ -37,13 +37,22 @@ if { [info exists FLASH_SIZE] } {
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
- # this is the SW-DP tap id not the jtag tap id
- set _CPUTAPID 0x0be12477
+ if { [using_jtag] } {
+ # See GD32E50x User Manual section 12.2.3
+ set _CPUTAPID 0x790007A3
+ } {
+ # this is the SW-DP tap id not the jtag tap id
+ set _CPUTAPID 0x0be12477
+ }
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+if {[using_jtag]} {
+ jtag newtap $_CHIPNAME bs -irlen 5
+}
+
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
@@ -56,6 +65,10 @@ flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0
$_TARGETNAME
# SWD speed (may be updated to higher value in board config file)
adapter speed 1000
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
reset_config srst_nogate
if {![using_hla]} {
@@ -65,10 +78,6 @@ if {![using_hla]} {
}
$_TARGETNAME configure -event examine-end {
- # Debug clock enable
- # RCU_APB2EN |= DBGMCUEN
- mmw 0x40021018 0x00400000 0
-
# Stop watchdog counters during halt
# DBG_CTL |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD
mmw 0xE0044004 0x00000307 0
--
