--- ** [tickets:#341] Semihosting for Cortex-A leads to halting upon non-semihosting SVCs** **Status:** new **Milestone:** 0.11.0 **Created:** Mon Feb 28, 2022 11:16 AM UTC by Alexander Kucherov **Last Updated:** Mon Feb 28, 2022 11:16 AM UTC **Owner:** nobody The current implementation of semihosting for Cortex-A setups SVC vector catch in DBGVCR, but "arm_semihosting()" handler processes only SVC instructions with semihosting values (0xAB for Thumb, 0x123456 for ARM) and ignores SVC with other values. When loaded image uses SVC also for purpose(s) other than semihosting (e.g. RTOS system calls), the execution is halted upon non-semihosting SVC and cannot be resumed unless semihosting is disabled. See the example below: - Execution has stopped at 0x14018a28 (SVC vector). - Last executed instruction (at LR-2) is "SVC 0xFD" (0xDFFD). - Execution cannot be continued (neither "resume" nor "step" command lead to change of PC). - Disabling of semihosting allows to continue execution (PC changed after "step" command). ~~~ > resume AMLR1.cpu.0 rev 1, partnum c09, arch f, variant 4, implementor 41 target halted in Thumb state due to undefined, current mode: Supervisor cpsr: 0x000001f3 pc: 0x14018a28, semihosting MMU: enabled, D-Cache: enabled, I-Cache: enabled > reg ===== ARM registers (0) r0 (/32): 0x00000001 (dirty) (1) r1 (/32): 0x1407a199 (dirty) (2) r2 (/32): 0x1401f054 (3) r3 (/32): 0x1400037c (4) r4 (/32): 0x00000001 (5) r5 (/32): 0x00000001 (6) r6 (/32): 0xa5a5a5a5 (7) r7 (/32): 0xa5a5a5a5 (8) r8 (/32): 0x00000004 (9) r9 (/32): 0xa5a5a5a5 (10) r10 (/32): 0xa5a5a5a5 (11) r11 (/32): 0xa5a5a5a5 (12) r12 (/32): 0x00000000 (13) sp_usr (/32) (14) lr_usr (/32) (15) pc (/32): 0x14018a28 (16) r8_fiq (/32) (17) r9_fiq (/32) (18) r10_fiq (/32) (19) r11_fiq (/32) (20) r12_fiq (/32) (21) sp_fiq (/32) (22) lr_fiq (/32) (23) sp_irq (/32) (24) lr_irq (/32) (25) sp_svc (/32): 0x1400037c (26) lr_svc (/32): 0x14018c6a (27) sp_abt (/32) (28) lr_abt (/32) (29) sp_und (/32) (30) lr_und (/32) (31) cpsr (/32): 0x000001f3 (32) spsr_fiq (/32) (33) spsr_irq (/32) (34) spsr_svc (/32): 0x000001f3 (35) spsr_abt (/32) (36) spsr_und (/32) (37) sp (/32) (38) lr (/32) (39) sp_mon (/32) (40) lr_mon (/32) (41) spsr_mon (/32) (44) d0 (/64) (45) d1 (/64) (46) d2 (/64) (47) d3 (/64) (48) d4 (/64) (49) d5 (/64) (50) d6 (/64) (51) d7 (/64) (52) d8 (/64) (53) d9 (/64) (54) d10 (/64) (55) d11 (/64) (56) d12 (/64) (57) d13 (/64) (58) d14 (/64) (59) d15 (/64) (60) d16 (/64) (61) d17 (/64) (62) d18 (/64) (63) d19 (/64) (64) d20 (/64) (65) d21 (/64) (66) d22 (/64) (67) d23 (/64) (68) d24 (/64) (69) d25 (/64) (70) d26 (/64) (71) d27 (/64) (72) d28 (/64) (73) d29 (/64) (74) d30 (/64) > mdh 0x14018c68 0x14018c68: dffd > resume AMLR1.cpu.0 rev 1, partnum c09, arch f, variant 4, implementor 41 target halted in Thumb state due to undefined, current mode: Supervisor cpsr: 0x000001f3 pc: 0x14018a28, semihosting MMU: enabled, D-Cache: enabled, I-Cache: enabled > step AMLR1.cpu.0 rev 1, partnum c09, arch f, variant 4, implementor 41 target halted in Thumb state due to undefined, current mode: Supervisor cpsr: 0x000001f3 pc: 0x14018a28, semihosting MMU: enabled, D-Cache: enabled, I-Cache: enabled > arm semihosting disable semihosting is disabled > step AMLR1.cpu.0 rev 1, partnum c09, arch f, variant 4, implementor 41 target halted in Thumb state due to breakpoint, current mode: Supervisor cpsr: 0x000001f3 pc: 0x14018b80 MMU: enabled, D-Cache: enabled, I-Cache: enabled > ~~~ --- Sent from sourceforge.net because openocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/ To unsubscribe from further messages, a project admin can change settings at https://sourceforge.net/p/openocd/admin/tickets/options. Or, if this is a mailing list, you can unsubscribe from the mailing list.
