This is an automated email from Gerrit.
"Steve Marple <stevemar...@googlemail.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/6941
-- gerrit
commit 537e0b4a83a28704c64d6e001c8506c8e85bc366
Author: Steve Marple <stevemar...@googlemail.com>
Date: Mon Apr 18 23:27:22 2022 +0100
Add AM335x driver for bitbang support on BeagleBones
Change-Id: Iac1c9f3d380e2474c8b77407c89c2aad96fbf2ea
Signed-off-by: Steve Marple <stevemar...@googlemail.com>
diff --git a/configure.ac b/configure.ac
index 15d7229a4f..6de8e12718 100644
--- a/configure.ac
+++ b/configure.ac
@@ -294,10 +294,14 @@ AS_CASE(["${host_cpu}"],
AC_ARG_ENABLE([imx_gpio],
AS_HELP_STRING([--enable-imx_gpio], [Enable building support for
bitbanging on NXP IMX processors]),
[build_imx_gpio=$enableval], [build_imx_gpio=no])
+ AC_ARG_ENABLE([am335xgpio],
+ AS_HELP_STRING([--enable-am335xgpio], [Enable building support for
bitbanging on AM335x (as found in Beaglebones)]),
+ [build_am335xgpio=$enableval], [build_am335xgpio=no])
],
[
build_bcm2835gpio=no
build_imx_gpio=no
+ build_am335xgpio=no
])
AS_CASE(["${host_cpu}"],
@@ -503,6 +507,13 @@ AS_IF([test "x$build_imx_gpio" = "xyes"], [
AC_DEFINE([BUILD_IMX_GPIO], [0], [0 if you don't want imx_gpio.])
])
+AS_IF([test "x$build_am335xgpio" = "xyes"], [
+ build_bitbang=yes
+ AC_DEFINE([BUILD_AM335XGPIO], [1], [1 if you want am335xgpio.])
+], [
+ AC_DEFINE([BUILD_AM335XGPIO], [0], [0 if you don't want am335xgpio.])
+])
+
AS_IF([test "x$parport_use_ppdev" = "xyes"], [
AC_DEFINE([PARPORT_USE_PPDEV], [1], [1 if you want parport to use ppdev.])
], [
@@ -706,6 +717,7 @@ AM_CONDITIONAL([EP93XX], [test "x$build_ep93xx" = "xyes"])
AM_CONDITIONAL([AT91RM9200], [test "x$build_at91rm9200" = "xyes"])
AM_CONDITIONAL([BCM2835GPIO], [test "x$build_bcm2835gpio" = "xyes"])
AM_CONDITIONAL([IMX_GPIO], [test "x$build_imx_gpio" = "xyes"])
+AM_CONDITIONAL([AM335XGPIO], [test "x$build_am335xgpio" = "xyes"])
AM_CONDITIONAL([BITBANG], [test "x$build_bitbang" = "xyes"])
AM_CONDITIONAL([JTAG_VPI], [test "x$build_jtag_vpi" = "xyes"])
AM_CONDITIONAL([VDEBUG], [test "x$build_vdebug" = "xyes"])
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 1b6d063028..1c881f51de 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -584,6 +584,9 @@ produced, PDF schematics are easily found and it is easy to
make.
@item @b{imx_gpio}
@* A NXP i.MX-based board (e.g. Wandboard) using the GPIO pins (should work on
any i.MX processor).
+@item @b{am335xgpio}
+@* A Texas Instruments AM335x-based board (e.g. BeagleBone Black) using the
GPIO pins of the expansion headers.
+
@item @b{jtag_vpi}
@* A JTAG driver acting as a client for the JTAG VPI server interface.
@* Link: @url{http://github.com/fjullien/jtag_vpi}
@@ -3313,6 +3316,83 @@ pinout.
@end deffn
+@deffn {Interface Driver} {am335xgpio} The AM335x SoC is present in BeagleBone
+Black and BeagleBone Green single-board computers which expose some of the
GPIOs
+on the two expansion headers.
+
+For maximum performance the driver accesses memory-mapped GPIO peripheral
+registers directly. The memory mapping requires read and write permission to
+kernel mmeory; if /dev/gpiomem exists it will be used, otherwise /dev/mem will
+be used. The driver restores the pin direction state on exit.
+
+All four GPIO ports are available. GPIOs numbered 0 to 31 are mapped to GPIO
port
+0, GPIO numbers 32 to 63 are mapped to GPIO port 1 and so on.
+
+See @file{interface/beaglebone-native.cfg} for a sample configuration file.
+
+@deffn {Config Command} {am335xgpio jtag_nums} @var{tck} @var{tms} @var{tdi}
@var{tdo}
+Set JTAG transport GPIO numbers for TCK, TMS, TDI, and TDO (in that order).
+Must be specified to enable JTAG transport. These pins can also be specified
+individually.
+@end deffn
+
+@deffn {Config Command} {am335xgpio tck_num} @var{tck}
+Set TCK GPIO number. Must be specified to enable JTAG transport. Can also be
+specified using the configuration command @command{am335xgpio jtag_nums}.
+@end deffn
+
+@deffn {Config Command} {am335xgpio tms_num} @var{tms}
+Set TMS GPIO number. Must be specified to enable JTAG transport. Can also be
+specified using the configuration command @command{am335xgpio jtag_nums}.
+@end deffn
+
+@deffn {Config Command} {am335xgpio tdo_num} @var{tdo}
+Set TDO GPIO number. Must be specified to enable JTAG transport. Can also be
+specified using the configuration command @command{am335xgpio jtag_nums}.
+@end deffn
+
+@deffn {Config Command} {am335xgpio tdi_num} @var{tdi}
+Set TDI GPIO number. Must be specified to enable JTAG transport. Can also be
+specified using the configuration command @command{am335xgpio jtag_nums}.
+@end deffn
+
+@deffn {Config Command} {am335xgpio swd_nums} @var{swclk} @var{swdio}
+Set SWD transport GPIO numbers for SWCLK and SWDIO (in that order). Must be
+specified to enable SWD transport. These pins can also be specified
individually.
+@end deffn
+
+@deffn {Config Command} {am335xgpio swclk_num} @var{swclk}
+Set SWCLK GPIO number. Must be specified to enable SWD transport. Can also be
+specified using the configuration command @command{am335xgpio swd_nums}.
+@end deffn
+
+@deffn {Config Command} {am335xgpio swdio_num} @var{swdio}
+Set SWDIO GPIO number. Must be specified to enable SWD transport. Can also be
+specified using the configuration command @command{am335xgpio swd_nums}.
+@end deffn
+
+@deffn {Config Command} {am335xgpio swdio_dir_num} @var{swdio} @var{dir}
+Set SWDIO direction control pin GPIO number. If specified, this pin can be used
+to control the direction of an external buffer on the SWDIO pin (set=output
+mode, clear=input mode). If not specified, this feature is disabled.
+@end deffn
+
+@deffn {Config Command} {am335xgpio srst_num} @var{srst}
+Set SRST GPIO number. Must be specified to enable SRST.
+@end deffn
+
+@deffn {Config Command} {am335xgpio trst_num} @var{trst}
+Set TRST GPIO number. Must be specified to enable TRST.
+@end deffn
+
+@deffn {Config Command} {am335xgpio speed_coeffs} @var{speed_coeff}
@var{speed_offset}
+Set SPEED_COEFF and SPEED_OFFSET for delay calculations. If unspecified
+speed_coeff defaults to 600000 and speed_offset defaults to 575.
+@end deffn
+
+@end deffn
+
+
@deffn {Interface Driver} {linuxgpiod}
Linux provides userspace access to GPIO through libgpiod since Linux kernel
version v4.6.
The driver emulates either JTAG and SWD transport through bitbanging.
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index 887f99bcd2..d05b7b9764 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -185,6 +185,9 @@ endif
if XDS110
DRIVERFILES += %D%/xds110.c
endif
+if AM335XGPIO
+DRIVERFILES += %D%/am335xgpio.c
+endif
DRIVERHEADERS = \
%D%/bitbang.h \
diff --git a/src/jtag/drivers/am335xgpio.c b/src/jtag/drivers/am335xgpio.c
new file mode 100644
index 0000000000..65d0b4f1cf
--- /dev/null
+++ b/src/jtag/drivers/am335xgpio.c
@@ -0,0 +1,650 @@
+/***************************************************************************
+ * Copyright (C) 2022 by Steve Marple, stevemar...@googlemail.com *
+ * *
+ * Based on bcm2835gpio.c and linuxgpiod.c *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <jtag/interface.h>
+#include <transport/transport.h>
+#include "bitbang.h"
+
+#include <sys/mman.h>
+
+/*
+ * GPIO register base addresses. Values taken from AM335x and AMIC110 Sitara
+ * Processors Technical Reference Manual, Chapter 2 Memory Map.
+ */
+#define AM335X_NUM_GPIO_PORTS 4
+#define AM335X_GPIO0_ADDR 0x44E07000
+#define AM335X_GPIO1_ADDR 0x4804C000
+#define AM335X_GPIO2_ADDR 0x481AC000
+#define AM335X_GPIO3_ADDR 0x481AE000
+
+/* 32-bit offsets from GPIO port base address */
+#define AM335X_GPIO_OE_OFFSET (0x134 / 4)
+#define AM335X_GPIO_DATAIN_OFFSET (0x138 / 4)
+#define AM335X_GPIO_CLEARDATAOUT_OFFSET (0x190 / 4)
+#define AM335X_GPIO_SETDATAOUT_OFFSET (0x194 / 4)
+
+#define AM335X_PORT(gpio_num) ((gpio_num) / 32)
+#define AM335X_BIT(gpio_num) ((gpio_num) % 32)
+#define AM335X_BIT_MASK(gpio_num) (1 << AM335X_BIT(gpio_num))
+
+/* AM335x uses 0 for output, 1 for input */
+#define SET_GPIO_INPUT(gpio_num) set_gpio_mode((gpio_num), 1)
+#define SET_GPIO_OUTPUT(gpio_num) set_gpio_mode((gpio_num), 0)
+
+static const uint32_t am335x_gpio_port_addresses[AM335X_NUM_GPIO_PORTS] = {
+ AM335X_GPIO0_ADDR,
+ AM335X_GPIO1_ADDR,
+ AM335X_GPIO2_ADDR,
+ AM335X_GPIO3_ADDR,
+};
+
+/* Memory-mapped address pointers */
+static uint32_t *am335x_gpio_base[AM335X_NUM_GPIO_PORTS];
+
+static int dev_mem_fd;
+
+static bb_value_t am335xgpio_read(void);
+static int am335xgpio_write(int tck, int tms, int tdi);
+
+static int am335xgpio_swdio_read(void);
+static void am335xgpio_swdio_drive(bool is_output);
+static int am335xgpio_swd_write(int swclk, int swdio);
+static int am335xgpio_blink(int on);
+
+static int am335xgpio_init(void);
+static int am335xgpio_quit(void);
+
+static struct bitbang_interface am335xgpio_bitbang = {
+ .read = am335xgpio_read,
+ .write = am335xgpio_write,
+ .swdio_read = am335xgpio_swdio_read,
+ .swdio_drive = am335xgpio_swdio_drive,
+ .swd_write = am335xgpio_swd_write,
+ .blink = am335xgpio_blink
+};
+
+/* GPIO numbers for each signal. Negative values are invalid */
+static int tck_gpio = -1;
+static int tck_gpio_mode;
+static int tms_gpio = -1;
+static int tms_gpio_mode;
+static int tdi_gpio = -1;
+static int tdi_gpio_mode;
+static int tdo_gpio = -1;
+static int tdo_gpio_mode;
+static int trst_gpio = -1;
+static int trst_gpio_mode;
+static int srst_gpio = -1;
+static int srst_gpio_mode;
+static int swclk_gpio = -1;
+static int swclk_gpio_mode;
+static int swdio_gpio = -1;
+static int swdio_gpio_mode;
+static int swdio_dir_gpio = -1;
+static int swdio_dir_gpio_mode;
+static int led_gpio = -1;
+static int led_gpio_mode = -1;
+
+static bool swdio_dir_is_active_high = true; /* Active state means output */
+static bool led_is_active_high = true;
+
+/* Transition delay coefficients */
+static int speed_coeff = 600000;
+static int speed_offset = 575;
+static unsigned int jtag_delay;
+
+static int is_gpio_valid(int gpio_num)
+{
+ return gpio_num >= 0 && gpio_num < (32 * AM335X_NUM_GPIO_PORTS);
+}
+
+static int get_gpio_mode(int gpio_num)
+{
+ return (*(am335x_gpio_base[AM335X_PORT(gpio_num)] +
AM335X_GPIO_OE_OFFSET) & AM335X_BIT_MASK(gpio_num))
+ >> AM335X_BIT(gpio_num);
+}
+
+static void set_gpio_mode(int gpio_num, int gpio_mode)
+{
+ if (gpio_mode)
+ (*(am335x_gpio_base[AM335X_PORT(gpio_num)] +
AM335X_GPIO_OE_OFFSET)) |= AM335X_BIT_MASK(gpio_num);
+ else
+ (*(am335x_gpio_base[AM335X_PORT(gpio_num)] +
AM335X_GPIO_OE_OFFSET)) &= (~AM335X_BIT_MASK(gpio_num));
+}
+
+static int get_gpio(int gpio_num)
+{
+ return (*(am335x_gpio_base[AM335X_PORT(gpio_num)] +
AM335X_GPIO_DATAIN_OFFSET) & AM335X_BIT_MASK(gpio_num))
+ >> AM335X_BIT(gpio_num);
+}
+
+static void set_gpio(int gpio_num, int value)
+{
+ if (value)
+ (*(am335x_gpio_base[AM335X_PORT(gpio_num)] +
AM335X_GPIO_SETDATAOUT_OFFSET)) = AM335X_BIT_MASK(gpio_num);
+ else
+ (*(am335x_gpio_base[AM335X_PORT(gpio_num)] +
AM335X_GPIO_CLEARDATAOUT_OFFSET)) = AM335X_BIT_MASK(gpio_num);
+}
+
+static bb_value_t am335xgpio_read(void)
+{
+ return get_gpio(tdo_gpio) ? BB_HIGH : BB_LOW;
+}
+
+static int am335xgpio_write(int tck, int tms, int tdi)
+{
+ set_gpio(tdi_gpio, tdi);
+ set_gpio(tms_gpio, tms);
+ set_gpio(tck_gpio, tck); /* Write clock last */
+
+ for (unsigned int i = 0; i < jtag_delay; ++i)
+ asm volatile ("");
+
+ return ERROR_OK;
+}
+
+static int am335xgpio_swd_write(int swclk, int swdio)
+{
+ set_gpio(swdio_gpio, swdio);
+ set_gpio(swclk_gpio, swclk); /* Write clock last */
+
+ for (unsigned int i = 0; i < jtag_delay; ++i)
+ asm volatile ("");
+
+ return ERROR_OK;
+}
+
+/* (1) assert or (0) deassert reset lines */
+static int am335xgpio_reset(int trst, int srst)
+{
+ if (is_gpio_valid(srst_gpio))
+ set_gpio(srst_gpio, srst ? 0 : 1); /* assume active low */
+
+ if (is_gpio_valid(trst_gpio))
+ set_gpio(trst_gpio, trst ? 0 : 1); /* assume active low */
+
+ return ERROR_OK;
+}
+
+static void am335xgpio_swdio_drive(bool is_output)
+{
+ if (is_output) {
+ set_gpio(swdio_dir_gpio, swdio_dir_is_active_high ? 1 : 0);
+ SET_GPIO_OUTPUT(swdio_gpio);
+ } else {
+ SET_GPIO_INPUT(swdio_gpio);
+ set_gpio(swdio_dir_gpio, swdio_dir_is_active_high ? 0 : 1);
+ }
+}
+
+static int am335xgpio_swdio_read(void)
+{
+ return get_gpio(swdio_gpio);
+}
+
+static int am335xgpio_blink(int on)
+{
+ if (is_gpio_valid(led_gpio))
+ set_gpio(led_gpio, (!on ^ led_is_active_high) ? 1 : 0);
+
+ return ERROR_OK;
+}
+
+static int am335xgpio_khz(int khz, int *jtag_speed)
+{
+ if (!khz) {
+ LOG_DEBUG("RCLK not supported");
+ return ERROR_FAIL;
+ }
+ *jtag_speed = speed_coeff/khz - speed_offset;
+ if (*jtag_speed < 0)
+ *jtag_speed = 0;
+ return ERROR_OK;
+}
+
+static int am335xgpio_speed_div(int speed, int *khz)
+{
+ *khz = speed_coeff/(speed + speed_offset);
+ return ERROR_OK;
+}
+
+static int am335xgpio_speed(int speed)
+{
+ jtag_delay = speed;
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_jtag_gpionums)
+{
+ if (CMD_ARGC == 4) {
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio);
+ } else if (CMD_ARGC != 0) {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ command_print(CMD,
+ "AM335x GPIO config: tck = %d, tms = %d, tdi = %d, tdo
= %d",
+ tck_gpio, tms_gpio, tdi_gpio, tdo_gpio);
+ return ERROR_OK;
+}
+
+
+COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tck)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
+
+ command_print(CMD, "AM335x GPIO config: tck = %d", tck_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tms)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tms_gpio);
+
+ command_print(CMD, "AM335x GPIO config: tms = %d", tms_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tdo)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdo_gpio);
+
+ command_print(CMD, "AM335x GPIO config: tdo = %d", tdo_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_tdi)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdi_gpio);
+
+ command_print(CMD, "AM335x GPIO config: tdi = %d", tdi_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_srst)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], srst_gpio);
+
+ command_print(CMD, "AM335x GPIO config: srst = %d", srst_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_jtag_gpionum_trst)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], trst_gpio);
+
+ command_print(CMD, "AM335x GPIO config: trst = %d", trst_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_swd_gpionums)
+{
+ if (CMD_ARGC == 2) {
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], swdio_gpio);
+ } else if (CMD_ARGC != 0) {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ command_print(CMD,
+ "AM335x GPIO nums: swclk = %d, swdio = %d",
+ swclk_gpio, swdio_gpio);
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_swd_gpionum_swclk)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
+
+ command_print(CMD, "AM335x num: swclk = %d", swclk_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_swd_gpionum_swdio)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_gpio);
+
+ command_print(CMD, "AM335x num: swdio = %d", swdio_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_swd_dir_gpionum_swdio)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_dir_gpio);
+
+ command_print(CMD, "AM335x num: swdio_dir = %d", swdio_dir_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_gpionum_led)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], led_gpio);
+
+ command_print(CMD, "AM335x num: led = %d", led_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(am335xgpio_handle_speed_coeffs)
+{
+ if (CMD_ARGC == 2) {
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], speed_coeff);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], speed_offset);
+ }
+
+ command_print(CMD, "AM335x GPIO: speed_coeffs = %d, speed_offset = %d",
+ speed_coeff, speed_offset);
+ return ERROR_OK;
+}
+
+static const struct command_registration am335xgpio_subcommand_handlers[] = {
+ {
+ .name = "jtag_nums",
+ .handler = am335xgpio_handle_jtag_gpionums,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio numbers for tck, tms, tdi, tdo. (in that order)",
+ .usage = "[tck tms tdi tdo]",
+ },
+ {
+ .name = "tck_num",
+ .handler = am335xgpio_handle_jtag_gpionum_tck,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for tck.",
+ .usage = "[tck]",
+ },
+ {
+ .name = "tms_num",
+ .handler = am335xgpio_handle_jtag_gpionum_tms,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for tms.",
+ .usage = "[tms]",
+ },
+ {
+ .name = "tdo_num",
+ .handler = am335xgpio_handle_jtag_gpionum_tdo,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for tdo.",
+ .usage = "[tdo]",
+ },
+ {
+ .name = "tdi_num",
+ .handler = am335xgpio_handle_jtag_gpionum_tdi,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for tdi.",
+ .usage = "[tdi]",
+ },
+ {
+ .name = "swd_nums",
+ .handler = am335xgpio_handle_swd_gpionums,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio numbers for swclk, swdio. (in that order)",
+ .usage = "[swclk swdio]",
+ },
+ {
+ .name = "swclk_num",
+ .handler = am335xgpio_handle_swd_gpionum_swclk,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for swclk.",
+ .usage = "[swclk]",
+ },
+ {
+ .name = "swdio_num",
+ .handler = am335xgpio_handle_swd_gpionum_swdio,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for swdio.",
+ .usage = "[swdio]",
+ },
+ {
+ .name = "swdio_dir_num",
+ .handler = am335xgpio_handle_swd_dir_gpionum_swdio,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for swdio direction control pin
(set=output mode, clear=input mode)",
+ .usage = "[swdio_dir]",
+ },
+ {
+ .name = "srst_num",
+ .handler = am335xgpio_handle_jtag_gpionum_srst,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for srst.",
+ .usage = "[srst]",
+ },
+ {
+ .name = "trst_num",
+ .handler = am335xgpio_handle_jtag_gpionum_trst,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for trst.",
+ .usage = "[trst]",
+ },
+ {
+ .name = "led_num",
+ .handler = am335xgpio_handle_gpionum_led,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for LED.",
+ .usage = "[led]",
+ },
+ {
+ .name = "speed_coeffs",
+ .handler = am335xgpio_handle_speed_coeffs,
+ .mode = COMMAND_CONFIG,
+ .help = "SPEED_COEFF and SPEED_OFFSET for delay calculations.",
+ .usage = "[SPEED_COEFF SPEED_OFFSET]",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration am335xgpio_command_handlers[] = {
+ {
+ .name = "am335xgpio",
+ .mode = COMMAND_ANY,
+ .help = "perform am335xgpio management",
+ .chain = am335xgpio_subcommand_handlers,
+ .usage = "",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const char * const am335x_transports[] = { "jtag", "swd", NULL };
+
+static struct jtag_interface am335xgpio_interface = {
+ .supported = DEBUG_CAP_TMS_SEQ,
+ .execute_queue = bitbang_execute_queue,
+};
+
+struct adapter_driver am335xgpio_adapter_driver = {
+ .name = "am335xgpio",
+ .transports = am335x_transports,
+ .commands = am335xgpio_command_handlers,
+
+ .init = am335xgpio_init,
+ .quit = am335xgpio_quit,
+ .reset = am335xgpio_reset,
+ .speed = am335xgpio_speed,
+ .khz = am335xgpio_khz,
+ .speed_div = am335xgpio_speed_div,
+
+ .jtag_ops = &am335xgpio_interface,
+ .swd_ops = &bitbang_swd,
+};
+
+static bool am335xgpio_jtag_mode_possible(void)
+{
+ if (!is_gpio_valid(tck_gpio))
+ return false;
+ if (!is_gpio_valid(tms_gpio))
+ return false;
+ if (!is_gpio_valid(tdi_gpio))
+ return false;
+ if (!is_gpio_valid(tdo_gpio))
+ return false;
+ return true;
+}
+
+static bool am335xgpio_swd_mode_possible(void)
+{
+ if (!is_gpio_valid(swclk_gpio))
+ return false;
+ if (!is_gpio_valid(swdio_gpio))
+ return false;
+ return true;
+}
+
+static int am335xgpio_init(void)
+{
+ bitbang_interface = &am335xgpio_bitbang;
+
+ LOG_INFO("AM335x GPIO JTAG/SWD bitbang driver");
+
+ if (transport_is_jtag() && !am335xgpio_jtag_mode_possible()) {
+ LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ if (transport_is_swd() && !am335xgpio_swd_mode_possible()) {
+ LOG_ERROR("Require swclk and swdio gpio for SWD mode");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ dev_mem_fd = open("/dev/gpiomem", O_RDWR | O_SYNC);
+ if (dev_mem_fd < 0) {
+ LOG_DEBUG("Cannot open /dev/gpiomem, fallback to /dev/mem");
+ dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
+ }
+ if (dev_mem_fd < 0) {
+ LOG_ERROR("open: %s", strerror(errno));
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ for (unsigned int i = 0; i < AM335X_NUM_GPIO_PORTS; ++i) {
+ am335x_gpio_base[i] = mmap(NULL, sysconf(_SC_PAGE_SIZE),
PROT_READ | PROT_WRITE,
+ MAP_SHARED, dev_mem_fd,
am335x_gpio_port_addresses[i]);
+
+ if (am335x_gpio_base[i] == MAP_FAILED) {
+ LOG_ERROR("mmap: %s", strerror(errno));
+ close(dev_mem_fd);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+ }
+
+ /*
+ * Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST
+ * as outputs. Drive TDI and TCK low, and TMS high.
+ */
+ if (transport_is_jtag()) {
+ tdo_gpio_mode = get_gpio_mode(tdo_gpio);
+ tdi_gpio_mode = get_gpio_mode(tdi_gpio);
+ tck_gpio_mode = get_gpio_mode(tck_gpio);
+ tms_gpio_mode = get_gpio_mode(tms_gpio);
+
+ SET_GPIO_INPUT(tdo_gpio);
+
+ set_gpio(tdi_gpio, 0);
+ set_gpio(tck_gpio, 0);
+ set_gpio(tms_gpio, 1);
+
+ SET_GPIO_OUTPUT(tdi_gpio);
+ SET_GPIO_OUTPUT(tck_gpio);
+ SET_GPIO_OUTPUT(tms_gpio);
+
+ /* Make TRST inactive */
+ if (is_gpio_valid(trst_gpio)) {
+ trst_gpio_mode = get_gpio_mode(trst_gpio);
+ set_gpio(trst_gpio, 1);
+ SET_GPIO_OUTPUT(trst_gpio);
+ }
+ }
+
+ if (transport_is_swd()) {
+ swclk_gpio_mode = get_gpio_mode(swclk_gpio);
+ swdio_gpio_mode = get_gpio_mode(swdio_gpio);
+ if (is_gpio_valid(swdio_dir_gpio)) {
+ swdio_dir_gpio_mode = get_gpio_mode(swdio_dir_gpio);
+ set_gpio(swdio_dir_gpio, swdio_dir_is_active_high ? 1 :
0);
+ SET_GPIO_OUTPUT(swdio_dir_gpio);
+ }
+
+ set_gpio(swdio_gpio, 0);
+ set_gpio(swclk_gpio, 0);
+
+ SET_GPIO_OUTPUT(swdio_gpio);
+ SET_GPIO_OUTPUT(swclk_gpio);
+ }
+
+ /* Make SRST inactive */
+ if (is_gpio_valid(srst_gpio)) {
+ trst_gpio_mode = get_gpio_mode(srst_gpio);
+ set_gpio(srst_gpio, 1);
+ SET_GPIO_OUTPUT(srst_gpio);
+ }
+
+ if (is_gpio_valid(led_gpio)) {
+ led_gpio_mode = get_gpio_mode(led_gpio);
+ set_gpio(led_gpio, led_is_active_high ? 0 : 1);
+ SET_GPIO_OUTPUT(led_gpio);
+ }
+
+ LOG_DEBUG("saved pinmux settings: tck %d tms %d tdi %d "
+ "tdo %d trst %d srst %d", tck_gpio_mode, tms_gpio_mode,
+ tdi_gpio_mode, tdo_gpio_mode, trst_gpio_mode, srst_gpio_mode);
+
+ return ERROR_OK;
+}
+
+static int am335xgpio_quit(void)
+{
+ if (transport_is_jtag()) {
+ set_gpio_mode(tdo_gpio, tdo_gpio_mode);
+ set_gpio_mode(tdi_gpio, tdi_gpio_mode);
+ set_gpio_mode(tck_gpio, tck_gpio_mode);
+ set_gpio_mode(tms_gpio, tms_gpio_mode);
+ if (is_gpio_valid(trst_gpio))
+ set_gpio_mode(trst_gpio, trst_gpio_mode);
+ }
+
+ if (transport_is_swd()) {
+ set_gpio_mode(swclk_gpio, swclk_gpio_mode);
+ set_gpio_mode(swdio_gpio, swdio_gpio_mode);
+ if (is_gpio_valid(swdio_dir_gpio))
+ set_gpio_mode(swdio_dir_gpio, swdio_dir_gpio_mode);
+ }
+
+ if (is_gpio_valid(srst_gpio))
+ set_gpio_mode(srst_gpio, srst_gpio_mode);
+
+ if (is_gpio_valid(led_gpio))
+ set_gpio_mode(led_gpio, led_gpio_mode);
+
+ return ERROR_OK;
+}
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index ddf70cc240..dc65e40282 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -150,7 +150,9 @@ extern struct adapter_driver stlink_dap_adapter_driver;
#if BUILD_RSHIM == 1
extern struct adapter_driver rshim_dap_adapter_driver;
#endif
-
+#if BUILD_AM335XGPIO == 1
+extern struct adapter_driver am335xgpio_adapter_driver;
+#endif
/**
* The list of built-in JTAG interfaces, containing entries for those
* drivers that were enabled by the @c configure script.
@@ -264,5 +266,9 @@ struct adapter_driver *adapter_drivers[] = {
#if BUILD_RSHIM == 1
&rshim_dap_adapter_driver,
#endif
+#if BUILD_AM335XGPIO == 1
+ &am335xgpio_adapter_driver,
+#endif
+
NULL,
};
diff --git a/tcl/interface/beaglebone-native.cfg
b/tcl/interface/beaglebone-native.cfg
new file mode 100644
index 0000000000..c49f5e14c1
--- /dev/null
+++ b/tcl/interface/beaglebone-native.cfg
@@ -0,0 +1,26 @@
+# BeagleBone native GPIO interface
+#
+# This is best used with a fast buffer but it is also suitable for a direct
+# connection if the target voltage matches the host's IO voltage (typically
+# 3.3V) and the cable is short.
+#
+# DO NOT APPLY VOLTAGE TO THE GPIO PINS UNTIL SYS_RESETN IS HIGH.
+#
+# Do not forget the GND connection,
+
+adapter driver am335xgpio
+
+# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
+# These depend on the system clock, calibrated for stock 1 GHz BeagleBoneBlack
+# am335xgpio speed SPEED_COEFF SPEED_OFFSET
+am335xgpio speed_coeffs 600000 575
+
+am335xgpio swclk_num 2
+am335xgpio swdio_num 4
+am335xgpio swdio_dir_num 60
+
+# USR0 LED
+am335xgpio led_num 53
+
+am335xgpio srst_num 65
+reset_config srst_only srst_push_pull
--
