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"Tarek BOCHKATI <tarek.bouchk...@gmail.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/6950
-- gerrit
commit 1efe79cfad938e12a4bcacea16162145046d1aef
Author: Tarek BOCHKATI <tarek.bouchk...@gmail.com>
Date: Thu Apr 28 03:46:35 2022 +0100
cortex_m: add detection of MVE feature for Armv8.1-M cores
For Armv8.1-M based cores, detect if the core implements the optional
M-profile vector extension (MVE), using MVFR1 register.
While at there rework armv7m->fp_feature detection based on MVFR0
and MVFR1 registers.
Change-Id: I92d5b1759aea9f7561d285f46acdec51d6efb7b4
Signed-off-by: Tarek BOCHKATI <tarek.bouchk...@gmail.com>
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 9ac121ac31..87bf46f0ce 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -222,6 +222,8 @@ enum {
FPV4_SP,
FPV5_SP,
FPV5_DP,
+ FPV5_MVE_I,
+ FPV5_MVE_F,
};
#define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 344cfcf617..55446a9de2 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2248,16 +2248,13 @@ static void cortex_m_dwt_free(struct target *target)
cm->dwt_cache = NULL;
}
-#define MVFR0 0xe000ef40
-#define MVFR1 0xe000ef44
+#define MVFR0 0xe000ef40
+#define MVFR1 0xe000ef44
-#define MVFR0_DEFAULT_M4 0x10110021
-#define MVFR1_DEFAULT_M4 0x11000011
-
-#define MVFR0_DEFAULT_M7_SP 0x10110021
-#define MVFR0_DEFAULT_M7_DP 0x10110221
-#define MVFR1_DEFAULT_M7_SP 0x11000011
-#define MVFR1_DEFAULT_M7_DP 0x12000011
+#define MVFR0_SP 0x00000020
+#define MVFR0_DP 0x00000200
+#define MVFR1_MVE_I 0x00000100
+#define MVFR1_MVE_F 0x00000200
static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
struct adiv5_ap **debug_ap)
@@ -2343,22 +2340,33 @@ int cortex_m_examine(struct target *target)
target_read_u32(target, MVFR0, &mvfr0);
target_read_u32(target, MVFR1, &mvfr1);
- /* test for floating point feature on Cortex-M4 */
- if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 ==
MVFR1_DEFAULT_M4)) {
- LOG_TARGET_DEBUG(target, "%s floating point
feature FPv4_SP found", cortex_m->core_info->name);
+ if ((mvfr0 & MVFR0_SP) == MVFR0_SP) {
+ LOG_TARGET_DEBUG(target, "%s floating point
feature FPv4_SP found",
+ cortex_m->core_info->name);
armv7m->fp_feature = FPV4_SP;
}
} else if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV5) {
target_read_u32(target, MVFR0, &mvfr0);
target_read_u32(target, MVFR1, &mvfr1);
- /* test for floating point features on Cortex-M7 */
- if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 ==
MVFR1_DEFAULT_M7_SP)) {
- LOG_TARGET_DEBUG(target, "%s floating point
feature FPv5_SP found", cortex_m->core_info->name);
+ if ((mvfr0 & MVFR0_DP) == MVFR0_DP) {
+ if ((mvfr1 & MVFR1_MVE_F) == MVFR1_MVE_F) {
+ LOG_TARGET_DEBUG(target, "%s floating
point feature FPv5_DP + MVE-F found",
+
cortex_m->core_info->name);
+ armv7m->fp_feature = FPV5_MVE_F;
+ } else {
+ LOG_TARGET_DEBUG(target, "%s floating
point feature FPv5_DP found",
+
cortex_m->core_info->name);
+ armv7m->fp_feature = FPV5_DP;
+ }
+ } else if ((mvfr0 & MVFR0_SP) == MVFR0_SP) {
+ LOG_TARGET_DEBUG(target, "%s floating point
feature FPv5_SP found",
+ cortex_m->core_info->name);
armv7m->fp_feature = FPV5_SP;
- } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 ==
MVFR1_DEFAULT_M7_DP)) {
- LOG_TARGET_DEBUG(target, "%s floating point
feature FPv5_DP found", cortex_m->core_info->name);
- armv7m->fp_feature = FPV5_DP;
+ } else if ((mvfr1 & MVFR1_MVE_I) == MVFR1_MVE_I) {
+ LOG_TARGET_DEBUG(target, "%s floating point
feature MVE-I found",
+ cortex_m->core_info->name);
+ armv7m->fp_feature = FPV5_MVE_I;
}
}
--
