This is an automated email from Gerrit.
"Tom Hebb <tommyh...@gmail.com>" just uploaded a new patch set to Gerrit, which
you can find at https://review.openocd.org/c/openocd/+/6959
-- gerrit
commit 78d6f0e323cbcac7eb98e76ca27d1a4b39fab48f
Author: Thomas Hebb <tommyh...@gmail.com>
Date: Fri Apr 29 23:26:00 2022 -0700
tcl/target/gd32vf103: copy a few minor settings from riscv-openocd
These changes bring over some lines from the independently-developed
gd32vf103.cfg that I contributed[1] to the riscv-openocd fork of
OpenOCD. They're all minor, so I'm squashing them into one review. The
changes are as follows:
- Mark that the chip's reset pin doesn't reset the debug module.
- Add boundary scan TAP.
- Mention inconsistency of CPU ID between vendor SDK and real hardware.
- Specify that there's no MMU so we don't look for one at runtime.
Signed-off-by: Thomas Hebb <tommyh...@gmail.com>
Change-Id: Ie8033eff436d6dbdc3eab156769a8908ccb547f6
diff --git a/tcl/target/gd32vf103.cfg b/tcl/target/gd32vf103.cfg
index 1b94773f6f..247271bbcd 100644
--- a/tcl/target/gd32vf103.cfg
+++ b/tcl/target/gd32vf103.cfg
@@ -21,11 +21,21 @@ if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE 0x1800
}
+reset_config srst_nogate
+
+# The vendor's configuration expects an ID of 0x1e200a6d, but this one is what
+# I have on my board (Sipeed Longan Nano, GD32VF103CBT6).
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+# Disable virtual address translation since we don't have an MMU. Nothing will
+# break without this line, but OpenOCD will do a few unnecessary register reads
+# to figure it out on its own.
+$_TARGETNAME riscv set_enable_virt2phys off
+
proc default_mem_access {} {
riscv set_mem_access progbuf
}
--
