[PATCH]: 28abd15ad4 target/riscv: fix 'reset run' after 'reset halt'

[gerrit]

This is an automated email from Gerrit.

"Tomas Vanek <van...@fbl.cz>" just uploaded a new patch set to Gerrit, which 
you can find at https://review.openocd.org/c/openocd/+/6961

-- gerrit

commit 28abd15ad4ff17c3da9d5d100a73cefa92739938
Author: Tomas Vanek <van...@fbl.cz>
Date:   Sun May 1 15:20:24 2022 +0200

    target/riscv: fix 'reset run' after 'reset halt'
    
    'reset halt' does not clear DM_DMCONTROL_HALTREQ at deassert_reset().
    If hw reset line is configured e.g. 'reset_config srst_only'
    the folowing 'reset run' halts:
    
     > gd32v.cpu curstate
     running
    
     > reset halt
     JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
     > gd32v.cpu curstate
     halted
    
     > reset
     JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
     > gd32v.cpu curstate
     halted <<<<---- wrong!!!
    
     > reset
     JTAG tap: gd32v.cpu tap/device found: 0x1000563d (mfg: 0x31e ...
     > gd32v.cpu curstate
     running
    
    Clear DM_DMCONTROL_HALTREQ when acking reset.
    
    Change-Id: Iae0454b425e81e64774b9785bb5ba1d4564d940b
    Signed-off-by: Tomas Vanek <van...@fbl.cz>

diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 2b9179d538..1b1450a7dc 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -2397,11 +2397,11 @@ static int deassert_reset(struct target *target)
        select_dmi(target);
 
        /* Clear the reset, but make sure haltreq is still set */
-       uint32_t control = 0;
-       control = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 
1 : 0);
+       uint32_t control = 0, control_haltreq;
        control = set_field(control, DM_DMCONTROL_DMACTIVE, 1);
+       control_haltreq = set_field(control, DM_DMCONTROL_HALTREQ, 
target->reset_halt ? 1 : 0);
        dmi_write(target, DM_DMCONTROL,
-                       set_hartsel(control, r->current_hartid));
+                       set_hartsel(control_haltreq, r->current_hartid));
 
        uint32_t dmstatus;
        int dmi_busy_delay = info->dmi_busy_delay;
@@ -2413,7 +2413,7 @@ static int deassert_reset(struct target *target)
                        if (index != target->coreid)
                                continue;
                        dmi_write(target, DM_DMCONTROL,
-                                       set_hartsel(control, index));
+                                       set_hartsel(control_haltreq, index));
                } else {
                        index = r->current_hartid;
                }
@@ -2449,7 +2449,7 @@ static int deassert_reset(struct target *target)
                target->state = TARGET_HALTED;
 
                if (get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET)) {
-                       /* Ack reset. */
+                       /* Ack reset and clear DM_DMCONTROL_HALTREQ if 
previously set */
                        dmi_write(target, DM_DMCONTROL,
                                        set_hartsel(control, index) |
                                        DM_DMCONTROL_ACKHAVERESET);

--