This is an automated email from Gerrit. "Erhan Kurubas <erhan.kuru...@espressif.com>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7020
-- gerrit commit 7dc7fef5af5e20e42e0bd5500a0eaf96fa229359 Author: Erhan Kurubas <erhan.kuru...@espressif.com> Date: Sun Jun 12 01:04:08 2022 +0200 esp32s2: convert counted timeout to timeval_ms Signed-off-by: Erhan Kurubas <erhan.kuru...@espressif.com> Change-Id: Id685408281478cec0e7e886dbedb3b8972c7b652 diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c index 212533ff8f..cacc5009ba 100644 --- a/src/target/espressif/esp32s2.c +++ b/src/target/espressif/esp32s2.c @@ -21,6 +21,7 @@ #include "config.h" #endif +#include <helper/time_support.h> #include "assert.h" #include <target/target.h> #include <target/target_type.h> @@ -482,15 +483,16 @@ static int esp32s2_soc_reset(struct target *target) } /* Wait for SoC to reset */ alive_sleep(100); - int timeout = 100; - while (target->state != TARGET_RESET && target->state != TARGET_RUNNING && --timeout > 0) { + int64_t timeout = timeval_ms() + 100; + while (target->state != TARGET_RESET && target->state != TARGET_RUNNING) { alive_sleep(10); xtensa_poll(target); + if (timeval_ms() >= timeout) { + LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state); + return ERROR_TARGET_TIMEOUT; + } } - if (timeout == 0) { - LOG_ERROR("Timed out waiting for CPU to be reset, target->state=%d", target->state); - return ERROR_TARGET_TIMEOUT; - } + xtensa_halt(target); res = target_wait_state(target, TARGET_HALTED, 1000); if (res != ERROR_OK) { --