This is an automated email from Gerrit.
"Jeremy Linton <lintonrjer...@gmail.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7053
-- gerrit
commit 401fcbea648a36c4391923da61e3d3ae965cbc81
Author: Jeremy Linton <lintonrjer...@gmail.com>
Date: Mon Jun 20 15:05:54 2022 -0500
target/armv8_opcodes: Add new sysregs and sysreg macro
The Arm reference manuals overwhelmingly provide the sysregs
in the form op0, op1, CRn, CRm, op2. Lets add a macro
to describe them this way so they can be quickly added
and compared against the manuals. Also a small comment tweak,
and a couple new system regs.
Signed-off-by: Jeremy Linton <lintonrjer...@gmail.com>
Change-Id: I1b9183088cd4e6e7c5c1a33268ee0359d4381f0b
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index 8c213ef4dd..3702944b9f 100644
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -34,6 +34,8 @@
#define SYSTEM_AAR64_MODE_EL3T 0xC
#define SYSTEM_AAR64_MODE_EL3H 0xd
+#define ARMV8_SYSREG(op0, op1, crn, crm, op2) ((op2) | (crm<<3) | (crn<<7) |
(op1<<11) | (op0<<14))
+
#define SYSTEM_DAIF 0b1101101000010001
#define SYSTEM_DAIF_MASK 0x3C0
#define SYSTEM_DAIF_SHIFT 6
@@ -64,6 +66,7 @@
#define SYSTEM_SPSR_EL3 0b1111001000000000
#define SYSTEM_ISR_EL1 0b1100011000001000
+#define SYSTEM_DISR_EL1 ARMV8_SYSREG(3,0,12,1,1)
#define SYSTEM_DBG_DSPSR_EL0 0b1101101000101000
#define SYSTEM_DBG_DLR_EL0 0b1101101000101001
@@ -83,7 +86,9 @@
#define SYSTEM_DCCVAU 0b0101101111011001
#define SYSTEM_DCCIVAC 0b0101101111110001
+#define SYSTEM_MIDR ARMV8_SYSREG(3,0,0,0,0)
#define SYSTEM_MPIDR 0b1100000000000101
+#define SYSTEM_REVIDR ARMV8_SYSREG(3,0,0,0,6)
#define SYSTEM_TCR_EL1 0b1100000100000010
#define SYSTEM_TCR_EL2 0b1110000100000010
@@ -137,6 +142,7 @@
#define ARMV8_ISB 0xd5033fdf
#define ARMV8_ISB_SY_T1 0xf3bf8f6f
+/* ARM V8 Move from system register. */
#define ARMV8_MRS(system, rt) (0xd5300000 | ((system) << 5) | (rt))
/* ARM V8 Move to system register. */
#define ARMV8_MSR_GP(system, rt) \
--
