This is an automated email from Gerrit.
"Ian Thompson <ia...@cadence.com>" just uploaded a new patch set to Gerrit,
which you can find at https://review.openocd.org/c/openocd/+/7083
-- gerrit
commit 7257f4ff9952d7746bf0b02d7cdf25975b02b7a3
Author: Ian Thompson <ia...@cadence.com>
Date: Sun Jul 10 17:35:50 2022 -0700
Generic Xtensa target config files
- Add new Xtensa TCL board files
- Add new Xtensa KC705 on-board FTDI interface
- Add new generic Xtensa and VDebug Xtensa target files
Signed-off-by: Ian Thompson <ia...@cadence.com>
Change-Id: I4acb15c83d1b7b8e6063833ce829530cb22a795e
diff --git a/tcl/board/xtensa-kc705-flyswatter2.cfg
b/tcl/board/xtensa-kc705-flyswatter2.cfg
new file mode 100644
index 0000000000..dcfc993473
--- /dev/null
+++ b/tcl/board/xtensa-kc705-flyswatter2.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with on-board (FTDI) adapter or various external adapters
+#
+
+source [find interface/ftdi/flyswatter2.cfg]
+adapter speed 10000
+
+# KC705 supports JTAG only
+transport select jtag
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/tcl/board/xtensa-kc705-jlink.cfg b/tcl/board/xtensa-kc705-jlink.cfg
new file mode 100644
index 0000000000..52d91ee28d
--- /dev/null
+++ b/tcl/board/xtensa-kc705-jlink.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with external J-Link adapters
+#
+
+# Adapter serial number specified in interface .cfg file
+source [find interface/jlink.cfg]
+adapter speed 10000
+
+# KC705 supports JTAG only
+transport select jtag
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/tcl/board/xtensa-kc705-onboard.cfg
b/tcl/board/xtensa-kc705-onboard.cfg
new file mode 100644
index 0000000000..f0a616cd7d
--- /dev/null
+++ b/tcl/board/xtensa-kc705-onboard.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence KC705 FPGA Development Platform for Xtensa targets
+# Can be used with on-board (FTDI) adapter or various external adapters
+#
+
+source [find interface/ftdi/xt_kc705_ml605.cfg]
+adapter speed 10000
+
+# KC705 supports JTAG only
+transport select jtag
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
diff --git a/tcl/board/xtensa-palladium-vdebug.cfg
b/tcl/board/xtensa-palladium-vdebug.cfg
new file mode 100644
index 0000000000..d4a700e36d
--- /dev/null
+++ b/tcl/board/xtensa-palladium-vdebug.cfg
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+source [find interface/vdebug.cfg]
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+source [find target/vd_xtensa_jtag.cfg]
diff --git a/tcl/interface/ftdi/xt_kc705_ml605.cfg
b/tcl/interface/ftdi/xt_kc705_ml605.cfg
new file mode 100644
index 0000000000..8a4baa6fe0
--- /dev/null
+++ b/tcl/interface/ftdi/xt_kc705_ml605.cfg
@@ -0,0 +1,11 @@
+#
+# Xilinx KC705 / ML605 with Xtensa daughtercard; onboard USB/FT2232
+#
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+ftdi_serial ML605-3223
+
+ftdi_layout_init 0x0010 0x007b
+ftdi_layout_signal nTRST -data 0x0010
+ftdi_layout_signal nSRST -ndata 0x0020
diff --git a/tcl/target/vd_xtensa_jtag.cfg b/tcl/target/vd_xtensa_jtag.cfg
new file mode 100644
index 0000000000..88f5bcc076
--- /dev/null
+++ b/tcl/target/vd_xtensa_jtag.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+# TODO: Enable backdoor memory access
+# set _MEMSTART 0x00000000
+# set _MEMSIZE 0x100000
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path dut_top.JTAG 10ns
+# DMA Memories to access backdoor (up to 4)
+# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+
+# Configure Xtensa core parameters next
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
+
+# register target
+proc vdebug_examine_end {} {
+# vdebug register_target
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { vdebug_examine_end }
diff --git a/tcl/target/xtensa.cfg b/tcl/target/xtensa.cfg
new file mode 100644
index 0000000000..4647588a86
--- /dev/null
+++ b/tcl/target/xtensa.cfg
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Target Support for Xtensa Processors
+#
+
+set xtensa_ids { 0x120034e5 0x120134e5
+ 0x209034e5 0x209134e5 0x209234e5 0x209334e5
0x209434e5 0x209534e5 0x209634e5 0x209734e5
+ 0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5
0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5
+ 0x20b034e5 }
+set expected_xtensa_ids {}
+foreach i $xtensa_ids {
+ lappend expected_xtensa_ids -expected-id $i
+}
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME xtensa
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPARGLIST "-expected-id $CPUTAPID"
+} else {
+ set _CPUTAPARGLIST [join $expected_xtensa_ids]
+}
+
+set _TARGETNAME $_CHIPNAME
+set _CPU0NAME cpu
+set _TAPNAME $_CHIPNAME.$_CPU0NAME
+
+if { [info exists XTENSA_DAP] } {
+ source [find target/swj-dp.tcl]
+
+ if { [using_jtag] } {
+ # DAP/JTAG
+ eval swj_newdap $_CHIPNAME cpu -irlen 4 $_CPUTAPARGLIST
+ } else {
+ # DAP/SWD
+ eval swj_newdap $_CHIPNAME cpu -irlen 5 $_CPUTAPARGLIST
+ }
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+ set _TARGETNAME $_CHIPNAME.cpu
+ target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap
+} else {
+ # JTAG direct (without DAP)
+ eval jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 $_CPUTAPARGLIST
+ target create $_TARGETNAME xtensa -chain-position $_TAPNAME
+}
+
+$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
+
+gdb_report_register_access_error enable
--
