This is an automated email from Gerrit.
"Jacek Wuwer <jacek...@gmail.com>" just uploaded a new patch set to Gerrit,
which you can find at https://review.openocd.org/c/openocd/+/7149
-- gerrit
commit 430a3a6f33273cf0b3a71c86c62f72fb61c56189
Author: Jacek Wuwer <jacek...@gmail.com>
Date: Mon Aug 29 15:55:37 2022 +0200
jtag/vdebug: add target-related functionality
This change implements target-related functionality in the driver.
The backdoor memory access implementation overrides the target write_memory
The polling mechanism depends on the target state, both need target access.
Change-Id: I4c7c45d50088c88c5a7545c33c4b520390979a3e
Signed-off-by: Jacek Wuwer <jacek...@gmail.com>
diff --git a/src/jtag/drivers/vdebug.c b/src/jtag/drivers/vdebug.c
index 035c1bee26..93bfe1aa58 100644
--- a/src/jtag/drivers/vdebug.c
+++ b/src/jtag/drivers/vdebug.c
@@ -1,27 +1,6 @@
/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
-/*----------------------------------------------------------------------------
- * Copyright 2020-2022 Cadence Design Systems, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *----------------------------------------------------------------------------
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *----------------------------------------------------------------------------
-*/
+
+/* Copyright 2020-2022 Cadence Design Systems, Inc. */
/*!
* @file
@@ -68,13 +47,15 @@
#include "jtag/interface.h"
#include "jtag/commands.h"
#include "transport/transport.h"
+#include "target/target.h"
+#include "target/target_type.h"
#include "target/arm_adi_v5.h"
#include "helper/time_support.h"
#include "helper/replacements.h"
#include "helper/log.h"
#include "helper/list.h"
-#define VD_VERSION 44
+#define VD_VERSION 46
#define VD_BUFFER_LEN 4024
#define VD_CHEADER_LEN 24
#define VD_SHEADER_LEN 16
@@ -228,6 +209,10 @@ struct vd_client {
char server_name[32];
char bfm_path[128];
char mem_path[VD_MAX_MEMORIES][128];
+ enum target_state targ_state;
+ struct target *targ;
+ int (*targ_write_memory)(struct target *target, target_addr_t address,
+ uint32_t size,
uint32_t count, const uint8_t *buffer);
struct vd_rdata rdataq;
};
@@ -293,7 +278,7 @@ static int vdebug_socket_open(char *server_addr, uint32_t
port)
LOG_ERROR("socket_open: cannot resolve address %s, error %d",
server_addr, vdebug_socket_error());
rc = VD_ERR_SOC_ADDR;
} else {
- buf_set_u32((uint8_t *)ainfo->ai_addr->sa_data, 0, 16,
htons(port));
+ h_u16_to_be((uint8_t *)ainfo->ai_addr->sa_data, port);
if (connect(hsock, ainfo->ai_addr, sizeof(struct sockaddr)) <
0) {
LOG_ERROR("socket_open: cannot connect to %s:%d, error
%d", server_addr, port, vdebug_socket_error());
rc = VD_ERR_SOC_CONN;
@@ -419,8 +404,8 @@ int vdebug_run_jtag_queue(int hsock, struct vd_shm *pm,
unsigned int count)
tdi = (pm->wd8[waddr * 4] >> num_pre) | (pm->wd8[waddr * 4 + 1]
<< (8 - num_pre));
tms = (pm->wd8[waddr * 4 + 4] >> num_pre) | (pm->wd8[waddr * 4
+ 4 + 1] << (8 - num_pre));
LOG_DEBUG_IO("%04x L:%02d O:%05x @%03x DI:%02x MS:%02x DO:%02x",
- le_to_h_u16(pm->wid) - count + req, num,
(vdc.trans_first << 14) | (vdc.trans_last << 15),
- waddr - 2, tdi, tms, (tdo ? tdo[0] : 0xdd));
+ le_to_h_u16(pm->wid) - count + req,
num, (vdc.trans_first << 14) | (vdc.trans_last << 15),
+ waddr - 2, tdi, tms, (tdo ? tdo[0] :
0xdd));
waddr += hwords * 2; /* start of next request */
req += 1;
}
@@ -484,14 +469,14 @@ int vdebug_run_reg_queue(int hsock, struct vd_shm *pm,
unsigned int count)
memcpy(&data[j * awidth],
&pm->rd8[(rwords + j) * awidth], awidth);
}
LOG_DEBUG_IO("read %04x AS:%02x RG:%02x O:%05x @%03x
D:%08x", le_to_h_u16(pm->wid) - count + req,
- aspace, addr, (vdc.trans_first << 14) |
(vdc.trans_last << 15), waddr,
- (num ? le_to_h_u32(&pm->rd8[rwords * 4]) :
0xdead));
+ aspace, addr, (vdc.trans_first
<< 14) | (vdc.trans_last << 15), waddr,
+ (num ?
le_to_h_u32(&pm->rd8[rwords * 4]) : 0xdead));
rwords += num * wwidth;
waddr += sizeof(uint64_t) / 4; /* waddr past header */
} else {
LOG_DEBUG_IO("write %04x AS:%02x RG:%02x O:%05x @%03x
D:%08x", le_to_h_u16(pm->wid) - count + req,
- aspace, addr, (vdc.trans_first << 14) |
(vdc.trans_last << 15), waddr,
- le_to_h_u32(&pm->wd8[(waddr + num + 1) * 4]));
+ aspace, addr, (vdc.trans_first
<< 14) | (vdc.trans_last << 15), waddr,
+ le_to_h_u32(&pm->wd8[(waddr +
num + 1) * 4]));
waddr += sizeof(uint64_t) / 4 + (num * wwidth * awidth
+ 3) / 4;
}
req += 1;
@@ -514,7 +499,7 @@ int vdebug_run_reg_queue(int hsock, struct vd_shm *pm,
unsigned int count)
}
static int vdebug_open(int hsock, struct vd_shm *pm, const char *path,
- uint8_t type, uint32_t
period_ps, uint32_t sig_mask)
+ uint8_t type, uint32_t period_ps,
uint32_t sig_mask)
{
int rc = VD_ERR_NOT_OPEN;
@@ -557,8 +542,8 @@ static int vdebug_open(int hsock, struct vd_shm *pm, const
char *path,
INIT_LIST_HEAD(&vdc.rdataq.lh);
LOG_DEBUG("%s type %0x, period %dps, buffer %dx%dB signals r%04xw%04x",
- path, type, vdc.bfm_period, VD_BUFFER_LEN / vdc.buf_width,
- vdc.buf_width, vdc.sig_read, vdc.sig_write);
+ path, type, vdc.bfm_period, VD_BUFFER_LEN /
vdc.buf_width,
+ vdc.buf_width, vdc.sig_read, vdc.sig_write);
return ERROR_OK;
}
@@ -664,7 +649,7 @@ static int vdebug_jtag_shift_tap(int hsock, struct vd_shm
*pm, uint8_t num_pre,
} else if (4 * waddr + sizeof(uint64_t) + 8 * hwords > VD_BUFFER_LEN) {
/* this req does not fit, discard it */
LOG_ERROR("%04x L:%02d O:%05x @%04x too many bits to shift",
- le_to_h_u16(pm->wid), anum, (vdc.trans_first << 14) |
(vdc.trans_last << 15), waddr);
+ le_to_h_u16(pm->wid), anum, (vdc.trans_first
<< 14) | (vdc.trans_last << 15), waddr);
rc = ERROR_FAIL;
}
@@ -693,7 +678,6 @@ static int vdebug_jtag_shift_tap(int hsock, struct vd_shm
*pm, uint8_t num_pre,
if (i % 4 == 3)
j += 4;
}
-
if (tdi)
if (num + num_pre > bytes * tobits) /* in case 1
additional byte needed for TDI */
pm->wd8[j + i] = (tdi[i - 1] >> (8 - num_pre));
/* put last TDI bits there */
@@ -771,7 +755,7 @@ static int vdebug_reg_write(int hsock, struct vd_shm *pm,
const uint32_t reg,
}
static int vdebug_reg_read(int hsock, struct vd_shm *pm, const uint32_t reg,
- uint32_t *data, uint8_t
aspace, uint8_t f_last)
+ uint32_t *data, uint8_t
aspace, uint8_t f_last)
{
uint32_t waddr;
int rc = ERROR_OK;
@@ -835,7 +819,7 @@ static int vdebug_mem_open(int hsock, struct vd_shm *pm,
const char *path, uint8
vdc.mem_width[ndx] = le_to_h_u16(&pm->rd8[0]) / 8; /* memory
width in bytes */
vdc.mem_depth[ndx] = le_to_h_u32(&pm->rd8[4]); /* memory
depth in words */
LOG_DEBUG("%" PRIx8 ": %s memory %" PRIu32 "x%" PRIu32 "B,
buffer %" PRIu32 "x%" PRIu32 "B", ndx, path,
- vdc.mem_depth[ndx], vdc.mem_width[ndx], VD_BUFFER_LEN /
vdc.mem_width[ndx], vdc.mem_width[ndx]);
+ vdc.mem_depth[ndx], vdc.mem_width[ndx],
VD_BUFFER_LEN / vdc.mem_width[ndx], vdc.mem_width[ndx]);
}
return ERROR_OK;
@@ -853,6 +837,99 @@ static void vdebug_mem_close(int hsock, struct vd_shm *pm,
uint8_t ndx)
LOG_DEBUG("%" PRIx8 ": %s", ndx, vdc.mem_path[ndx]);
}
+static int vdebug_mem_write(int hsock, struct vd_shm *pm, uint8_t ndx,
+ uint64_t addr, uint32_t num, const uint8_t
*data)
+{
+ pm->cmd = VD_CMD_MEMWRITE;
+ h_u32_to_le(pm->rwdata, ndx); /* memory ID v43+ */
+ h_u16_to_le(pm->wbytes, num);
+ h_u16_to_le(pm->wwords, (num + vdc.mem_width[ndx] - 1) /
vdc.mem_width[ndx]);
+ h_u16_to_le(pm->rbytes, 0);
+ h_u16_to_le(pm->rwords, 0);
+ h_u32_to_le(pm->offset, addr / vdc.mem_width[ndx]);
+ h_u16_to_le(pm->offseth, (addr / vdc.mem_width[ndx]) >> 32);
+ memcpy(pm->wd8, data, num);
+ int rc = vdebug_wait_server(hsock, pm);
+ if (rc)
+ LOG_ERROR("0x%x writing %" PRIu32 " bytes at %" PRIx64, rc,
num, addr);
+ else
+ LOG_DEBUG("%" PRIx8 ": A:%08" PRIx64 " L:%" PRIu32 " D:%08x",
ndx, addr, num, le_to_h_u32(pm->wd8));
+
+ h_u32_to_le(pm->offset, 0);
+ h_u16_to_le(pm->offseth, 0);
+
+ return ERROR_OK;
+}
+
+/* function gets invoked through a callback every (vdc.poll_min +
vdc.poll_max) / 2
+ * if the data transfer functions took less than poll_min ms, measured by
targ_time
+ * wait function is called and its time measured and wait cycles adjusted.
+ * The wait allows hardware to advance, when no data activity from the vdebug
occurs
+ */
+static int vdebug_poll(void *priv)
+{
+ int64_t ts, te;
+ uint32_t cmdtime = 0;
+ struct target **t = priv;
+
+ if (*t && vdc.targ_state != (*t)->state) {
+ vdc.targ_state = (*t)->state;
+ vdc.poll_cycles = vdc.poll_max; /* reset polling when target
state changes */
+ }
+
+ if (vdc.targ_time < vdc.poll_min) {
+ ts = timeval_ms();
+ vdebug_wait(vdc.hsocket, pbuf, vdc.poll_cycles);
+ te = timeval_ms();
+ cmdtime = (uint32_t)(te - ts);
+ if (cmdtime < ((vdc.poll_min + vdc.poll_max) / 4))
+ vdc.poll_cycles *= 2;
+ else if (cmdtime > ((vdc.poll_min + vdc.poll_max) / 2))
+ vdc.poll_cycles /= 2;
+ } else if (vdc.targ_time > (vdc.poll_min + vdc.poll_max) / 2) {
+ vdc.poll_cycles /= 2;
+ }
+
+ LOG_DEBUG("poll after %" PRIu32 "ms in state %" PRIx8 "; wait %" PRIu32
" cycles in %" PRIu32 "ms",
+ vdc.targ_time, vdc.targ_state, vdc.poll_cycles, cmdtime);
+ vdc.targ_time = 0; /* reset target time counter */
+
+ return ERROR_OK;
+}
+
+static int vdebug_write_memory(struct target *pt, target_addr_t address,
+ uint32_t size,
uint32_t count, const uint8_t *buffer)
+{
+ uint8_t ndx;
+ uint32_t offset;
+ uint32_t written;
+ uint32_t towrite;
+ int rc = ERROR_OK;
+
+ for (ndx = 0; ndx < vdc.mem_ndx; ndx++)
+ if (vdc.mem_width[ndx] && address >= vdc.mem_base[ndx] &&
+ address + size * count <= vdc.mem_base[ndx] +
vdc.mem_size[ndx])
+ break; /* hit one of the declared memories */
+
+ if (ndx < vdc.mem_ndx && size * count > 4) {
+ offset = address - vdc.mem_base[ndx];
+ LOG_INFO("vdebug overloaded memory write i:%" PRIx8 " a:0x%08x
l:0x%" PRIx32,
+ ndx, vdc.mem_base[ndx] + offset, count * size);
+ written = 0;
+ while (!rc && written < count * size) {
+ towrite = (count * size - written < VD_BUFFER_LEN ?
count * size - written : VD_BUFFER_LEN);
+ rc = vdebug_mem_write(vdc.hsocket, pbuf, ndx, offset,
towrite, buffer + written);
+ offset += towrite;
+ written += towrite;
+ }
+ } else if (vdc.targ_write_memory) {
+ rc = vdc.targ_write_memory(pt, address, size, count, buffer);
+ }
+
+ LOG_DEBUG(TARGET_ADDR_FMT " n:%" PRIu32 " w:%" PRIu32, address, count,
size);
+
+ return rc;
+}
static int vdebug_init(void)
{
@@ -891,6 +968,8 @@ static int vdebug_init(void)
LOG_ERROR("0x%x cannot connect to %s", rc,
vdc.mem_path[i]);
}
+ target_register_timer_callback(vdebug_poll, (vdc.poll_min +
vdc.poll_max) / 2,
+
TARGET_TIMER_TYPE_PERIODIC, &vdc.targ);
LOG_INFO("vdebug %d connected to %s through %s:%" PRIu16,
VD_VERSION, vdc.bfm_path, vdc.server_name,
vdc.server_port);
}
@@ -900,6 +979,8 @@ static int vdebug_init(void)
static int vdebug_quit(void)
{
+ target_unregister_timer_callback(vdebug_poll, vdc.targ);
+ vdc.targ_write_memory = NULL; /* target is already destroyed at this
point */
for (uint8_t i = 0; i < vdc.mem_ndx; i++)
if (vdc.mem_width[i])
vdebug_mem_close(vdc.hsocket, pbuf, i);
@@ -1249,6 +1330,26 @@ COMMAND_HANDLER(vdebug_set_polling)
return ERROR_OK;
}
+COMMAND_HANDLER(vdebug_register_target)
+{
+ if (vdc.targ) {
+ LOG_WARNING("target already registered, ignoring");
+ } else {
+ vdc.targ = get_current_target(CMD_CTX); /* last or target
selected by targets cmd */
+ if (!vdc.targ) {
+ LOG_ERROR("cannot register target, no target specified
in the configuration?");
+ return ERROR_FAIL;
+ }
+ if (vdc.targ->type) {
+ vdc.targ_write_memory = vdc.targ->type->write_memory;
+ vdc.targ->type->write_memory = &vdebug_write_memory;
+ LOG_INFO("%s: %u target memories registered for direct
access", target_name(vdc.targ), vdc.mem_ndx);
+ }
+ }
+
+ return ERROR_OK;
+}
+
static const struct command_registration vdebug_command_handlers[] = {
{
.name = "server",
@@ -1285,6 +1386,13 @@ static const struct command_registration
vdebug_command_handlers[] = {
.help = "set the polling pause, executing hardware cycles
between min and max",
.usage = "<min cycles> <max cycles>",
},
+ {
+ .name = "register_target",
+ .handler = &vdebug_register_target,
+ .mode = COMMAND_EXEC,
+ .help = "Hook up the direct memory access and polling routines
to target",
+ .usage = "",
+ },
COMMAND_REGISTRATION_DONE
};
diff --git a/tcl/board/vd_a53x2_dap.cfg b/tcl/board/vd_a53x2_dap.cfg
index 4cf5594d32..43f321c2b8 100644
--- a/tcl/board/vd_a53x2_dap.cfg
+++ b/tcl/board/vd_a53x2_dap.cfg
@@ -27,3 +27,4 @@ source [find target/swj-dp.tcl]
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
source [find target/vd_aarch64.cfg]
+source [find target/vd_target_event.cfg]
diff --git a/tcl/board/vd_a53x2_jtag.cfg b/tcl/board/vd_a53x2_jtag.cfg
index a5e8d24e55..93aa465312 100644
--- a/tcl/board/vd_a53x2_jtag.cfg
+++ b/tcl/board/vd_a53x2_jtag.cfg
@@ -29,3 +29,4 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask
0xf -expected-id $_CP
jtag arp_init-reset
source [find target/vd_aarch64.cfg]
+source [find target/vd_target_event.cfg]
diff --git a/tcl/board/vd_m4_dap.cfg b/tcl/board/vd_m4_dap.cfg
index 691b6235f6..602be21df9 100644
--- a/tcl/board/vd_m4_dap.cfg
+++ b/tcl/board/vd_m4_dap.cfg
@@ -24,3 +24,4 @@ source [find target/swj-dp.tcl]
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
source [find target/vd_cortex_m.cfg]
+source [find target/vd_target_event.cfg]
diff --git a/tcl/board/vd_m4_jtag.cfg b/tcl/board/vd_m4_jtag.cfg
index 4c795ebfd0..6616b128c4 100644
--- a/tcl/board/vd_m4_jtag.cfg
+++ b/tcl/board/vd_m4_jtag.cfg
@@ -28,3 +28,4 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask
0xf -expected-id $_CP
jtag arp_init-reset
source [find target/vd_cortex_m.cfg]
+source [find target/vd_target_event.cfg]
diff --git a/tcl/board/vd_m7_jtag.cfg b/tcl/board/vd_m7_jtag.cfg
index 880ef9b4c2..da11200df5 100644
--- a/tcl/board/vd_m7_jtag.cfg
+++ b/tcl/board/vd_m7_jtag.cfg
@@ -28,3 +28,4 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask
0xf -expected-id $_CP
jtag arp_init-reset
source [find target/vd_cortex_m.cfg]
+source [find target/vd_target_event.cfg]
diff --git a/tcl/board/vd_pulpissimo_jtag.cfg b/tcl/board/vd_pulpissimo_jtag.cfg
index a3f5a84886..837dd1138c 100644
--- a/tcl/board/vd_pulpissimo_jtag.cfg
+++ b/tcl/board/vd_pulpissimo_jtag.cfg
@@ -30,3 +30,4 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask
0x1f -expected-id $_
jtag arp_init-reset
source [find target/vd_riscv.cfg]
+source [find target/vd_target_event.cfg]
diff --git a/tcl/board/vd_swerv_jtag.cfg b/tcl/board/vd_swerv_jtag.cfg
index c5d33f268a..d778624b5b 100644
--- a/tcl/board/vd_swerv_jtag.cfg
+++ b/tcl/board/vd_swerv_jtag.cfg
@@ -30,3 +30,4 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x01 -irmask
0x1f -expected-id $_
jtag arp_init-reset
source [find target/vd_riscv.cfg]
+source [find target/vd_target_event.cfg]
diff --git a/tcl/board/vd_xt8_jtag.cfg b/tcl/board/vd_xt8_jtag.cfg
new file mode 100644
index 0000000000..a68fb7ef8f
--- /dev/null
+++ b/tcl/board/vd_xt8_jtag.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Xtensa xt8 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME xt8
+set CPUTAPID 0x120034e5
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor, the values come from generated
xtensa-core-xt8.cfg
+#vdebug mem_path Testbench.Xtsubsystem.Core0.iram0.iram0.mem.dataArray
0x40000000 0x100000
+#vdebug mem_path Testbench.Xtsubsystem.Core0.dram0.dram0.mem.dataArray
0x3ff00000 0x40000
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
+source [find target/xtensa-core-xt8.cfg]
+
+source [find target/vd_target_event.cfg]
diff --git a/tcl/target/vd_target_event.cfg b/tcl/target/vd_target_event.cfg
new file mode 100644
index 0000000000..13c38be0a3
--- /dev/null
+++ b/tcl/target/vd_target_event.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface target event registration
+
+# register target
+proc vdebug_examine_end {} {
+ vdebug register_target
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { vdebug_examine_end }
diff --git a/tcl/target/vd_xtensa_jtag.cfg b/tcl/target/vd_xtensa_jtag.cfg
deleted file mode 100644
index 88f5bcc076..0000000000
--- a/tcl/target/vd_xtensa_jtag.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-# Cadence virtual debug interface
-# for Palladium emulation systems
-#
-
-# TODO: Enable backdoor memory access
-# set _MEMSTART 0x00000000
-# set _MEMSIZE 0x100000
-
-# BFM hierarchical path and input clk period
-vdebug bfm_path dut_top.JTAG 10ns
-# DMA Memories to access backdoor (up to 4)
-# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
-
-# Create Xtensa target first
-source [find target/xtensa.cfg]
-
-# Configure Xtensa core parameters next
-# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
-
-# register target
-proc vdebug_examine_end {} {
-# vdebug register_target
-}
-
-# Default hooks
-$_TARGETNAME configure -event examine-end { vdebug_examine_end }
diff --git a/tcl/target/xtensa-core-xt8.cfg b/tcl/target/xtensa-core-xt8.cfg
new file mode 100644
index 0000000000..c7b58b54b8
--- /dev/null
+++ b/tcl/target/xtensa-core-xt8.cfg
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# OpenOCD configuration file for Xtensa xt8 target
+
+# Core definition and ABI
+xtensa xtdef LX
+xtensa xtopt arnum 32
+xtensa xtopt windowed 1
+
+
+# Exception/Interrupt Options
+xtensa xtopt exceptions 1
+xtensa xtopt hipriints 1
+xtensa xtopt intlevels 3
+xtensa xtopt excmlevel 1
+
+
+# Cache Options
+xtensa xtmem icache 16 1024 1
+xtensa xtmem dcache 16 1024 1 1
+
+
+# Memory Options
+xtensa xtmem iram 0x40000000 1048576
+xtensa xtmem dram 0x3ff00000 262144
+xtensa xtmem srom 0x50000000 131072
+xtensa xtmem sram 0x60000000 4194304
+
+
+# Memory Protection/Translation Options
+
+
+# Debug Options
+xtensa xtopt debuglevel 3
+xtensa xtopt ibreaknum 2
+xtensa xtopt dbreaknum 2
+
+
+# Core Registers
+xtensa xtregs 127
+xtensa xtreg a0 0x0000
+xtensa xtreg a1 0x0001
+xtensa xtreg a2 0x0002
+xtensa xtreg a3 0x0003
+xtensa xtreg a4 0x0004
+xtensa xtreg a5 0x0005
+xtensa xtreg a6 0x0006
+xtensa xtreg a7 0x0007
+xtensa xtreg a8 0x0008
+xtensa xtreg a9 0x0009
+xtensa xtreg a10 0x000a
+xtensa xtreg a11 0x000b
+xtensa xtreg a12 0x000c
+xtensa xtreg a13 0x000d
+xtensa xtreg a14 0x000e
+xtensa xtreg a15 0x000f
+xtensa xtreg pc 0x0020
+xtensa xtreg ar0 0x0100
+xtensa xtreg ar1 0x0101
+xtensa xtreg ar2 0x0102
+xtensa xtreg ar3 0x0103
+xtensa xtreg ar4 0x0104
+xtensa xtreg ar5 0x0105
+xtensa xtreg ar6 0x0106
+xtensa xtreg ar7 0x0107
+xtensa xtreg ar8 0x0108
+xtensa xtreg ar9 0x0109
+xtensa xtreg ar10 0x010a
+xtensa xtreg ar11 0x010b
+xtensa xtreg ar12 0x010c
+xtensa xtreg ar13 0x010d
+xtensa xtreg ar14 0x010e
+xtensa xtreg ar15 0x010f
+xtensa xtreg ar16 0x0110
+xtensa xtreg ar17 0x0111
+xtensa xtreg ar18 0x0112
+xtensa xtreg ar19 0x0113
+xtensa xtreg ar20 0x0114
+xtensa xtreg ar21 0x0115
+xtensa xtreg ar22 0x0116
+xtensa xtreg ar23 0x0117
+xtensa xtreg ar24 0x0118
+xtensa xtreg ar25 0x0119
+xtensa xtreg ar26 0x011a
+xtensa xtreg ar27 0x011b
+xtensa xtreg ar28 0x011c
+xtensa xtreg ar29 0x011d
+xtensa xtreg ar30 0x011e
+xtensa xtreg ar31 0x011f
+xtensa xtreg lbeg 0x0200
+xtensa xtreg lend 0x0201
+xtensa xtreg lcount 0x0202
+xtensa xtreg sar 0x0203
+xtensa xtreg windowbase 0x0248
+xtensa xtreg windowstart 0x0249
+xtensa xtreg configid0 0x02b0
+xtensa xtreg configid1 0x02d0
+xtensa xtreg ps 0x02e6
+xtensa xtreg expstate 0x03e6
+xtensa xtreg mmid 0x0259
+xtensa xtreg ibreakenable 0x0260
+xtensa xtreg ddr 0x0268
+xtensa xtreg ibreaka0 0x0280
+xtensa xtreg ibreaka1 0x0281
+xtensa xtreg dbreaka0 0x0290
+xtensa xtreg dbreaka1 0x0291
+xtensa xtreg dbreakc0 0x02a0
+xtensa xtreg dbreakc1 0x02a1
+xtensa xtreg epc1 0x02b1
+xtensa xtreg epc2 0x02b2
+xtensa xtreg epc3 0x02b3
+xtensa xtreg depc 0x02c0
+xtensa xtreg eps2 0x02c2
+xtensa xtreg eps3 0x02c3
+xtensa xtreg excsave1 0x02d1
+xtensa xtreg excsave2 0x02d2
+xtensa xtreg excsave3 0x02d3
+xtensa xtreg interrupt 0x02e2
+xtensa xtreg intset 0x02e2
+xtensa xtreg intclear 0x02e3
+xtensa xtreg intenable 0x02e4
+xtensa xtreg exccause 0x02e8
+xtensa xtreg debugcause 0x02e9
+xtensa xtreg ccount 0x02ea
+xtensa xtreg icount 0x02ec
+xtensa xtreg icountlevel 0x02ed
+xtensa xtreg excvaddr 0x02ee
+xtensa xtreg ccompare0 0x02f0
+xtensa xtreg ccompare1 0x02f1
+xtensa xtreg pwrctl 0x200f
+xtensa xtreg pwrstat 0x2010
+xtensa xtreg eristat 0x2011
+xtensa xtreg cs_itctrl 0x2012
+xtensa xtreg cs_claimset 0x2013
+xtensa xtreg cs_claimclr 0x2014
+xtensa xtreg cs_lockaccess 0x2015
+xtensa xtreg cs_lockstatus 0x2016
+xtensa xtreg cs_authstatus 0x2017
+xtensa xtreg fault_info 0x2026
+xtensa xtreg trax_id 0x2027
+xtensa xtreg trax_control 0x2028
+xtensa xtreg trax_status 0x2029
+xtensa xtreg trax_data 0x202a
+xtensa xtreg trax_address 0x202b
+xtensa xtreg trax_pctrigger 0x202c
+xtensa xtreg trax_pcmatch 0x202d
+xtensa xtreg trax_delay 0x202e
+xtensa xtreg trax_memstart 0x202f
+xtensa xtreg trax_memend 0x2030
+xtensa xtreg pmg 0x203e
+xtensa xtreg pmpc 0x203f
+xtensa xtreg pm0 0x2040
+xtensa xtreg pm1 0x2041
+xtensa xtreg pmctrl0 0x2042
+xtensa xtreg pmctrl1 0x2043
+xtensa xtreg pmstat0 0x2044
+xtensa xtreg pmstat1 0x2045
+xtensa xtreg ocdid 0x2046
+xtensa xtreg ocd_dcrclr 0x2047
+xtensa xtreg ocd_dcrset 0x2048
+xtensa xtreg ocd_dsr 0x2049
+xtensa xtreg psintlevel 0x2003
+xtensa xtreg psum 0x2004
+xtensa xtreg pswoe 0x2005
+xtensa xtreg psexcm 0x2006
+xtensa xtreg pscallinc 0x2007
+xtensa xtreg psowb 0x2008
+
--
