This is an automated email from Gerrit.
"Mateus Campaner Hercules <mchercu...@gmail.com>" just uploaded a new patch set
to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7476
-- gerrit
commit 5e54d1ecce99cf45172cd7beb5315835be88b8bd
Author: Mateus Campaner Hercules <mchercu...@gmail.com>
Date: Wed Feb 15 12:04:53 2023 -0300
Adds FreeRTOS:MPU stackings of cortex-m3/cortex-m4
- Adds the FreeRTOS:MPU stack view without FPU usage
- Adds the FreeRTOS:MPU stack view with FPU usage
Signed-off-by: Mateus Campaner Hercules <mchercu...@gmail.com>
Change-Id: I06ef26c7e11506acccc41a198c57645f1bd68b5f
diff --git a/src/rtos/rtos_standard_stackings.c
b/src/rtos/rtos_standard_stackings.c
index 5478080cf7..1d96acd1c5 100644
--- a/src/rtos/rtos_standard_stackings.c
+++ b/src/rtos/rtos_standard_stackings.c
@@ -11,7 +11,6 @@
#include "rtos.h"
#include "target/armv7m.h"
-#include "rtos_standard_stackings.h"
static const struct stack_register_offset
rtos_standard_cortex_m3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
{ ARMV7M_R0, 0x20, 32 }, /* r0 */
@@ -73,6 +72,46 @@ static const struct stack_register_offset
rtos_standard_cortex_m4f_fpu_stack_off
{ ARMV7M_XPSR, 0x80, 32 }, /* xPSR */
};
+static const struct stack_register_offset
rtos_standard_cortex_m4f_mpu_stack_offsets[] = {
+ { ARMV7M_R0, 0x28, 32 }, /* r0 */
+ { ARMV7M_R1, 0x2c, 32 }, /* r1 */
+ { ARMV7M_R2, 0x30, 32 }, /* r2 */
+ { ARMV7M_R3, 0x34, 32 }, /* r3 */
+ { ARMV7M_R4, 0x04, 32 }, /* r4 */
+ { ARMV7M_R5, 0x08, 32 }, /* r5 */
+ { ARMV7M_R6, 0x0c, 32 }, /* r6 */
+ { ARMV7M_R7, 0x10, 32 }, /* r7 */
+ { ARMV7M_R8, 0x14, 32 }, /* r8 */
+ { ARMV7M_R9, 0x18, 32 }, /* r9 */
+ { ARMV7M_R10, 0x1c, 32 }, /* r10 */
+ { ARMV7M_R11, 0x20, 32 }, /* r11 */
+ { ARMV7M_R12, 0x38, 32 }, /* r12 */
+ { ARMV7M_R13, -2, 32 }, /* sp */
+ { ARMV7M_R14, 0x3c, 32 }, /* lr */
+ { ARMV7M_PC, 0x40, 32 }, /* pc */
+ { ARMV7M_XPSR, 0x44, 32 }, /* xPSR */
+};
+
+static const struct stack_register_offset
rtos_standard_cortex_m4f_mpu_fpu_stack_offsets[] = {
+ { ARMV7M_R0, 0x68, 32 }, /* r0 */
+ { ARMV7M_R1, 0x6c, 32 }, /* r1 */
+ { ARMV7M_R2, 0x70, 32 }, /* r2 */
+ { ARMV7M_R3, 0x74, 32 }, /* r3 */
+ { ARMV7M_R4, 0x04, 32 }, /* r4 */
+ { ARMV7M_R5, 0x08, 32 }, /* r5 */
+ { ARMV7M_R6, 0x0c, 32 }, /* r6 */
+ { ARMV7M_R7, 0x10, 32 }, /* r7 */
+ { ARMV7M_R8, 0x14, 32 }, /* r8 */
+ { ARMV7M_R9, 0x18, 32 }, /* r9 */
+ { ARMV7M_R10, 0x1c, 32 }, /* r10 */
+ { ARMV7M_R11, 0x20, 32 }, /* r11 */
+ { ARMV7M_R12, 0x78, 32 }, /* r12 */
+ { ARMV7M_R13, -2, 32 }, /* sp */
+ { ARMV7M_R14, 0x7c, 32 }, /* lr */
+ { ARMV7M_PC, 0x80, 32 }, /* pc */
+ { ARMV7M_XPSR, 0x84, 32 }, /* xPSR */
+};
+
static const struct stack_register_offset
rtos_standard_cortex_r4_stack_offsets[] = {
{ 0, 0x08, 32 }, /* r0 (a1) */
@@ -103,6 +142,45 @@ static const struct stack_register_offset
rtos_standard_cortex_r4_stack_offsets[
{ 26, 0x04, 32 }, /* CSPR */
};
+static const struct stack_register_offset
rtos_standard_nds32_n1068_stack_offsets[] = {
+ { 0, 0x88, 32 }, /* R0 */
+ { 1, 0x8C, 32 }, /* R1 */
+ { 2, 0x14, 32 }, /* R2 */
+ { 3, 0x18, 32 }, /* R3 */
+ { 4, 0x1C, 32 }, /* R4 */
+ { 5, 0x20, 32 }, /* R5 */
+ { 6, 0x24, 32 }, /* R6 */
+ { 7, 0x28, 32 }, /* R7 */
+ { 8, 0x2C, 32 }, /* R8 */
+ { 9, 0x30, 32 }, /* R9 */
+ { 10, 0x34, 32 }, /* R10 */
+ { 11, 0x38, 32 }, /* R11 */
+ { 12, 0x3C, 32 }, /* R12 */
+ { 13, 0x40, 32 }, /* R13 */
+ { 14, 0x44, 32 }, /* R14 */
+ { 15, 0x48, 32 }, /* R15 */
+ { 16, 0x4C, 32 }, /* R16 */
+ { 17, 0x50, 32 }, /* R17 */
+ { 18, 0x54, 32 }, /* R18 */
+ { 19, 0x58, 32 }, /* R19 */
+ { 20, 0x5C, 32 }, /* R20 */
+ { 21, 0x60, 32 }, /* R21 */
+ { 22, 0x64, 32 }, /* R22 */
+ { 23, 0x68, 32 }, /* R23 */
+ { 24, 0x6C, 32 }, /* R24 */
+ { 25, 0x70, 32 }, /* R25 */
+ { 26, 0x74, 32 }, /* R26 */
+ { 27, 0x78, 32 }, /* R27 */
+ { 28, 0x7C, 32 }, /* R28 */
+ { 29, 0x80, 32 }, /* R29 */
+ { 30, 0x84, 32 }, /* R30 (LP) */
+ { 31, 0x00, 32 }, /* R31 (SP) */
+ { 32, 0x04, 32 }, /* PSW */
+ { 33, 0x08, 32 }, /* IPC */
+ { 34, 0x0C, 32 }, /* IPSW */
+ { 35, 0x10, 32 }, /* IFC_LP */
+};
+
static target_addr_t rtos_generic_stack_align(struct target *target,
const uint8_t *stack_data, const struct rtos_register_stacking
*stacking,
target_addr_t stack_ptr, int align)
@@ -198,6 +276,24 @@ static target_addr_t
rtos_standard_cortex_m4f_fpu_stack_align(struct target *tar
stack_ptr, XPSR_OFFSET);
}
+static target_addr_t rtos_standard_cortex_m4f_mpu_stack_align(struct target
*target,
+ const uint8_t *stack_data, const struct rtos_register_stacking
*stacking,
+ target_addr_t stack_ptr)
+{
+ const int XPSR_OFFSET = 0x44;
+ return rtos_cortex_m_stack_align(target, stack_data, stacking,
+ stack_ptr, XPSR_OFFSET);
+}
+
+static target_addr_t rtos_standard_cortex_m4f_mpu_fpu_stack_align(struct
target *target,
+ const uint8_t *stack_data, const struct rtos_register_stacking
*stacking,
+ target_addr_t stack_ptr)
+{
+ const int XPSR_OFFSET = 0x84;
+ return rtos_cortex_m_stack_align(target, stack_data, stacking,
+ stack_ptr, XPSR_OFFSET);
+}
+
const struct rtos_register_stacking rtos_standard_cortex_m3_stacking = {
.stack_registers_size = 0x40,
@@ -223,6 +319,22 @@ const struct rtos_register_stacking
rtos_standard_cortex_m4f_fpu_stacking = {
.register_offsets = rtos_standard_cortex_m4f_fpu_stack_offsets
};
+const struct rtos_register_stacking rtos_standard_cortex_m4f_mpu_stacking = {
+ .stack_registers_size = 0x44,
+ .stack_growth_direction = -1,
+ .num_output_registers = ARMV7M_NUM_CORE_REGS,
+ .calculate_process_stack = rtos_standard_cortex_m4f_mpu_stack_align,
+ .register_offsets = rtos_standard_cortex_m4f_mpu_stack_offsets
+};
+
+const struct rtos_register_stacking rtos_standard_cortex_m4f_mpu_fpu_stacking
= {
+ .stack_registers_size = 0xcc,
+ .stack_growth_direction = -1,
+ .num_output_registers = ARMV7M_NUM_CORE_REGS,
+ .calculate_process_stack = rtos_standard_cortex_m4f_mpu_fpu_stack_align,
+ .register_offsets = rtos_standard_cortex_m4f_mpu_fpu_stack_offsets
+};
+
const struct rtos_register_stacking rtos_standard_cortex_r4_stacking = {
.stack_registers_size = 0x48,
.stack_growth_direction = -1,
@@ -230,3 +342,11 @@ const struct rtos_register_stacking
rtos_standard_cortex_r4_stacking = {
.calculate_process_stack = rtos_generic_stack_align8,
.register_offsets = rtos_standard_cortex_r4_stack_offsets
};
+
+const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking = {
+ .stack_registers_size = 0x90,
+ .stack_growth_direction = -1,
+ .num_output_registers = 32,
+ .calculate_process_stack = rtos_generic_stack_align8,
+ .register_offsets = rtos_standard_nds32_n1068_stack_offsets
+};
diff --git a/src/rtos/rtos_standard_stackings.h
b/src/rtos/rtos_standard_stackings.h
index 99fbe07e48..513644ebe9 100644
--- a/src/rtos/rtos_standard_stackings.h
+++ b/src/rtos/rtos_standard_stackings.h
@@ -13,6 +13,8 @@
extern const struct rtos_register_stacking rtos_standard_cortex_m3_stacking;
extern const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking;
extern const struct rtos_register_stacking
rtos_standard_cortex_m4f_fpu_stacking;
+extern const struct rtos_register_stacking
rtos_standard_cortex_m4f_mpu_stacking;
+extern const struct rtos_register_stacking
rtos_standard_cortex_m4f_mpu_fpu_stacking;
extern const struct rtos_register_stacking rtos_standard_cortex_r4_stacking;
target_addr_t rtos_generic_stack_align8(struct target *target,
const uint8_t *stack_data, const struct rtos_register_stacking
*stacking,
--
