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"Wolfram Sang <w...@kernel.org>" just uploaded a new patch set to Gerrit, which
you can find at https://review.openocd.org/c/openocd/+/7578
-- gerrit
commit 73cb0cc568f1cc54e099d006eea893d0ae4d81d3
Author: Wolfram Sang <w...@kernel.org>
Date: Tue Mar 28 21:28:35 2023 +0200
tcl/board/calao-usb-a9g20-c01: add proper initialization
Initialize clocks to max speed and setup SDRAM. NAND support is still
incomplete. Originally found at:
https://elinux.org/index.php?title=Calao_Atmel_AT91_development_board&oldid=73933
Updated the code from 2011 and improved it a bit.
Signed-off-by: Wolfram Sang <w...@kernel.org>
Change-Id: I83474e07c8de8cc3b5d058029551935549693ef9
diff --git a/tcl/board/calao-usb-a9g20-c01.cfg
b/tcl/board/calao-usb-a9g20-c01.cfg
index 6c4bd40fe9..d2017864a9 100644
--- a/tcl/board/calao-usb-a9g20-c01.cfg
+++ b/tcl/board/calao-usb-a9g20-c01.cfg
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# CALAO Systems USB-A9G20-C01
+# Authors: Gregory Hermant, Jean-Christophe PLAGNIOL-VILLARD, Wolfram Sang
adapter driver ftdi
ftdi device_desc "USB-A9G20"
@@ -12,3 +13,160 @@ ftdi layout_signal nSRST -data 0x0200 -noe 0x0800
transport select jtag
source [find target/at91sam9g20.cfg]
+source [find mem_helper.tcl]
+
+proc at91sam9g20_reset_start { } {
+
+ # Make sure that the jtag is running slow, since there are a number of
different ways the board
+ # can be configured coming into this state that can cause
communication problems with the jtag
+ # adapter. Also since this call can be made following a "reset init"
where fast memory accesses
+ # are enabled, Need to temporarily shut this down so that the RSTC_MR
register can be written at slower
+ # jtag speed without causing GDB keep alive problem.
+
+ arm7_9 fast_memory_access disable
+ adapter speed 2 ;# Slow-speed oscillator enabled at
reset, so run jtag speed slow.
+ halt 0 ;# Make sure processor is halted, or
error will result in following steps.
+ wait_halt 10000
+ # RSTC_MR : enable user reset, MMU may be enabled... use physical
address
+ mww phys 0xfffffd08 0xa5000501
+}
+
+proc at91sam9g20_reset_init { } {
+
+ # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift
over to a normal clock requires
+ # a number of steps that must be carefully performed. The process
outline below follows the
+ # recommended procedure outlined in the AT91SAM9G20 technical manual.
+ #
+ # Several key and very important things to keep in mind:
+ # The SDRAM parts used currently on the Atmel evaluation board are -75
grade parts. This
+ # means the master clock (MCLK) must be at or below 133 MHz or timing
errors will occur. The processor
+ # core can operate up to 400 MHz and therefore PCLK must be at or
below this to function properly.
+
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog.
+
+ # Set oscillator bypass bit (12.00 MHz external oscillator) in
CKGR_MOR register.
+
+ mww 0xfffffc20 0x00000002
+
+ # Set PLLA Register for 798.000 MHz (divider: bypass, multiplier: 132).
+ # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+ mww 0xfffffc28 0x20843F02
+ while { [expr { [mrw 0xfffffc68] & 0x02 } ] != 2 } { sleep 1 }
+
+ # Set master system clock prescaler divide by 6 and processor clock
divide by 2 in PMC_MCKR.
+ # Wait for MCKRDY signal from PMC_SR to assert.
+
+ mww 0xfffffc30 0x00001300
+ while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
+
+ # Now change PMC_MCKR register to select PLLA.
+ # Wait for MCKRDY signal from PMC_SR to assert.
+
+ mww 0xfffffc30 0x00001302
+ while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }
+
+ # Processor and master clocks are now operating and stable at maximum
frequency possible:
+ # -> MCLK = 133.000 MHz
+ # -> PCLK = 400.000 MHz
+
+ # Switch to fast JTAG speed
+
+ adapter speed 9500
+
+ # Enable faster DCC downloads.
+
+ arm7_9 dcc_downloads enable
+ arm7_9 fast_memory_access enable
+
+ # To be able to use external SDRAM, several peripheral configuration
registers must
+ # be modified. The first change is made to PIO_ASR to select
peripheral functions
+ # for D15 through D31. The second change is made to the PIO_PDR
register to disable
+ # this for D15 through D31.
+
+ mww 0xfffff870 0xffff0000
+ mww 0xfffff804 0xffff0000
+
+ # The EBI chip select register EBI_CS must be specifically configured
to enable the internal SDRAM controller
+ # using CS1. Additionally we want CS3 assigned to NandFlash. Also
VDDIO is connected physically on
+ # the board to the 1.8V VDC power supply so set the appropriate
register bit to notify the micrcontroller.
+
+ mww 0xffffef1c 0x000000a
+
+ # The USB-A9G20 Embedded computer has built-in NandFlash. The exact
physical timing characteristics
+ # for the memory type used on the current board (MT29F2G08AACWP) can
be established by setting
+ # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and
SMC_MODE3.
+
+ mww 0xffffec30 0x00020002
+ mww 0xffffec34 0x04040404
+ mww 0xffffec38 0x00070007
+ mww 0xffffec3c 0x00030003
+
+ # Now setup SDRAM. This is tricky and configuration is very important
for reliability! The current calculations
+ # are based on 2 x Micron LPSDRAM MT48H16M16LFBF-75 memory (4 M x 16
bit x 4 banks). If you use this file as a reference
+ # for a new board that uses different SDRAM devices or clock rates,
you need to recalculate the value inserted
+ # into the SDRAM_CR register. Using the memory datasheet for the -75
grade part and assuming a master clock
+ # of 133.000 MHz then the SDCLK period is equal to 7.6 ns. This means
the device requires:
+ #
+ # CAS latency = 3 cycles
+ # TXSR = 10 cycles
+ # TRAS = 6 cycles
+ # TRCD = 3 cycles
+ # TRP = 3 cycles
+ # TRC = 9 cycles
+ # TWR = 2 cycles
+ # 9 column, 13 row, 4 banks
+ # refresh equal to or less then 7.8 us for commercial/industrial
rated devices
+ #
+ # Thus SDRAM_CR = 0xa6339279
+
+ mww 0xffffea08 0xa6339279
+
+ # Memory Device Type: SDRAM (low-power would be 0x1)
+ mww 0xffffea24 0x00000000
+
+ # Next issue a 'NOP' command through the SDRAMC_MR register followed
by writing a zero value into
+ # the starting memory location for the SDRAM.
+
+ mww 0xffffea00 0x00000001
+ mww 0x20000000 0
+
+ # Issue an 'All Banks Precharge' command through the SDRAMC_MR
register followed by writing a zero
+ # value into the starting memory location for the SDRAM.
+
+ mww 0xffffea00 0x00000002
+ mww 0x20000000 0
+
+ # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.
Follow this operation by writing
+ # zero values eight times into the starting memory location for the
SDRAM.
+
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+ mww 0x20000000 0
+
+ # Almost done, so next issue a 'Load Mode Register' command followed
by a zero value write to the
+ # the starting memory location for the SDRAM.
+
+ mww 0xffffea00 0x3
+ mww 0x20000000 0
+
+ # Signal normal mode using the SDRAMC_MR register and follow with a
zero value write the starting
+ # memory location for the SDRAM.
+
+ mww 0xffffea00 0x0
+ mww 0x20000000 0
+
+ # Finally set the refresh rate to about every 7 us (7.5 ns x 924
cycles).
+
+ mww 0xffffea04 0x0000039c
+}
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
+$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
--
