This is an automated email from Gerrit.
"Tarek BOCHKATI <tarek.bouchk...@gmail.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7694
-- gerrit
commit 66fb88773359bb8ee121f8b3ea0259ede045f9cd
Author: Tarek BOCHKATI <tarek.bouchk...@st.com>
Date: Wed May 31 15:16:35 2023 +0100
flash/stm32l4x: support STM32WBA5xx devices
STM32WBA5x have a single bank flash up to 1MB
Change-Id: I3d720e202f0fdd89ecd8aa7224653ca5a7ae187b
Signed-off-by: Tarek BOCHKATI <tarek.bouchk...@st.com>
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index b9ce7f19dc..c720b2ceb7 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -360,6 +360,10 @@ static const struct stm32l4_rev stm32u59_u5axx_revs[] = {
{ 0x3000, "C" }, { 0x3001, "X" },
};
+static const struct stm32l4_rev stm32wba5x_revs[] = {
+ { 0x1000, "A" },
+};
+
static const struct stm32l4_rev stm32wb1xx_revs[] = {
{ 0x1000, "A" }, { 0x2000, "B" },
};
@@ -617,6 +621,18 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.otp_base = 0x0BFA0000,
.otp_size = 512,
},
+ {
+ .id = DEVID_STM32WBA5X,
+ .revs = stm32wba5x_revs,
+ .num_revs = ARRAY_SIZE(stm32wba5x_revs),
+ .device_str = "STM32WBA5x",
+ .max_flash_size_kb = 1024,
+ .flags = F_QUAD_WORD_PROG | F_HAS_TZ |
F_HAS_L5_FLASH_REGS,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x0FF907A0,
+ .otp_base = 0x0FF90000,
+ .otp_size = 512,
+ },
{
.id = DEVID_STM32WB1XX,
.revs = stm32wb1xx_revs,
@@ -2043,6 +2059,12 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_info->bank1_sectors = num_pages / 2;
}
break;
+ case DEVID_STM32WBA5X:
+ /* single bank flash */
+ page_size_kb = 8;
+ num_pages = flash_size_kb / page_size_kb;
+ stm32l4_info->bank1_sectors = num_pages;
+ break;
case DEVID_STM32WB5XX:
case DEVID_STM32WB3XX:
/* single bank flash */
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index 910da7ff9a..5f3bc26576 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -105,6 +105,7 @@
#define DEVID_STM32G49_G4AXX 0x479
#define DEVID_STM32U59_U5AXX 0x481
#define DEVID_STM32U57_U58XX 0x482
+#define DEVID_STM32WBA5X 0x492
#define DEVID_STM32WB1XX 0x494
#define DEVID_STM32WB5XX 0x495
#define DEVID_STM32WB3XX 0x496
diff --git a/tcl/target/stm32wbax.cfg b/tcl/target/stm32wbax.cfg
new file mode 100644
index 0000000000..74fe370da5
--- /dev/null
+++ b/tcl/target/stm32wbax.cfg
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32wbax family
+
+#
+# stm32wba devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32wbax
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ if { [using_jtag] } {
+ set _CPUTAPID 0x6ba00477
+ } else {
+ # SWD IDCODE (single drop, arm)
+ set _CPUTAPID 0x6ba02477
+ }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+ jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num
1
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size
$_WORKAREASIZE -work-area-backup 0
+
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+ # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+ # Configure system to use MSI 24 MHz clock, compliant with VOS default
Range1.
+ # 2 WS compliant with VOS=Range1 and 24 MHz.
+ # mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTBE | 2(Latency)
+ # mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+ # Boost JTAG frequency
+ # adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+ # Reset clock is MSI (4 MHz)
+ # adapter speed 500
+}
+
+$_TARGETNAME configure -event examine-end {
+ # Enable debug during low power modes (uses more power)
+ # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+ mmw 0xE0042004 0x00000006 0
+
+ # Stop watchdog counters during halt
+ # DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
+ mmw 0xE0042008 0x00001800 0
+}
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0040000
--
