This is an automated email from Gerrit.
"Artemiy Volkov <arte...@synopsys.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7767
-- gerrit
commit df9f5863fd7ea3b81f9da3c5de3fadd55fcc64c0
Author: Artemiy Volkov <arte...@synopsys.com>
Date: Thu Jul 6 13:25:00 2023 +0200
target/arc: do not invalidate icache when (un)setting breakpoints
Currently, instruction cache is being invalidated in
arc_{un,}set_breakpoint() regardless of whether the breakpoint's type is
HW or SW. For SW breakpoints, this has no net effect as the caches are
flushed prior to resuming execution anyway and is thus merely
unnecessary; but for HW breakpoints this invalidation is not preceded by
a flush and might lead to loss of data. This patch removes the
invalidate() call altogether to correct this undesired behavior for HW
breakpoints.
With this patch applied, all supported HW breakpoint tests from the gdb
testsuite are now passing with the arc-openocd backend.
Change-Id: I3d252b97f01f1a1e2bf0eb8fb257bdab0c544bc2
Signed-off-by: Artemiy Volkov <arte...@synopsys.com>
diff --git a/src/target/arc.c b/src/target/arc.c
index 9ae3ae6104..11a891161e 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -1577,9 +1577,6 @@ static int arc_set_breakpoint(struct target *target,
return ERROR_FAIL;
}
- /* core instruction cache is now invalid. */
- CHECK_RETVAL(arc_cache_invalidate(target));
-
return ERROR_OK;
}
@@ -1662,9 +1659,6 @@ static int arc_unset_breakpoint(struct target *target,
return ERROR_FAIL;
}
- /* core instruction cache is now invalid. */
- CHECK_RETVAL(arc_cache_invalidate(target));
-
return retval;
}
--
