I was ignoring the errata, as it's titled "single stepping", which is not Liviu's case. But reading it carefully, under "Conditions" that can trigger the issue there is "The processor exits Debug state." So we could assume that at the resume from a semihosting BKPT, a SysTick interrupt is pending and the resume triggers immediately the halt inside the interrupt handler. It could be interesting to test with -c 'init;cortex_m maskisr on' on the command line. The command maskisr is not available in HLA mode and has to executed after init.
Antonio On Tue, Jul 11, 2023 at 9:13 AM Tomas Vanek <tom_...@users.sourceforge.net> wrote: > > On 11/07/2023 08:13, Liviu Ionescu wrote: > > > >> On 11 Jul 2023, at 08:44, Tomas Vanek <tom_...@users.sourceforge.net> > >> wrote: > >> > >> Couldn't it be related to the MASKINTS erratum of Cortex-M7 r0p1 ... > > I checked the 'STM32F76xxx/77xxx device errata', ES0334 - Rev 9 - December > > 2022, but could not find anything related. > > > > > > Liviu > > > It is a problem in the ARM licensed silicon so it may or more likely may > not be described in ST device errata. > ARM doc: > https://developer.arm.com/documentation/EPM064408/latest/ > 702596 > Single stepping Cortex-M7 enters pending exception handler > > and check OpenOCD debug log what product revision is the Cortex-M7 core. > > If OpenOCD detects M7 r0p1 (or r0p0), enables lot of workarounds by > setting cortex_m->maskints_erratum. > Be aware that there is no complete workaround for this erratum, so > OpenOCD just minimizes the time window > when single stepping can enter a pending interrupt handler. It could > cause the OpenOCD host speed dependency you > described. > > I'm not familiar with the details of semihosting implementation, I > assume that the semihosting BKPT must be > overcome by single step like any other BKPT. > > T >
