This is an automated email from Gerrit.
"Michael Chalfant <michael.chalf...@gmail.com>" just uploaded a new patch set
to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7820
-- gerrit
commit 581926dd35fe1c1ff7accdf520f7a5dd031ca7c5
Author: Michael Chalfant <michael.chalf...@gmail.com>
Date: Fri Jul 21 07:16:59 2023 -0700
arm_opcode: Add support for ARM MCRR/MRRC
Add support for the ARM MCRR/MRRC instructions which require the use of
two registers to transfer a 64-bit co-processor registers. We are going
to use this in a subsequent patch in order to properly dump 64-bit page
table descriptors that exist on ARMv7A with VMSA extensions.
We make use of r0 and r1 to transfer 64-bit quantities to/from DCC.
Change-Id: Ice6e404898cb5ccef800e8e8af5514b8e7f5e2f3
Signed-off-by: Florian Fainelli <f.faine...@gmail.com>
Signed-off-by: Michael Chalfant <michael.chalf...@gmail.com>
diff --git a/src/target/arm.h b/src/target/arm.h
index bd65db2436..cf6d58fc15 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -226,7 +226,7 @@ struct arm {
/** Read coprocessor to two registers. */
int (*mrrc)(struct target *target, int cpnum,
- uint32_t op, uint32_t CRm,
+ uint32_t op, uint32_t crm,
uint64_t *value);
/** Write coprocessor register. */
@@ -237,7 +237,7 @@ struct arm {
/** Write coprocessor from two registers. */
int (*mcrr)(struct target *target, int cpnum,
- uint32_t op, uint32_t CRm,
+ uint32_t op, uint32_t crm,
uint64_t value);
void *arch_info;
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index ad84c072d4..bcd7f30b89 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -64,7 +64,7 @@ static int dpm_mrc(struct target *target, int cpnum,
}
static int dpm_mrrc(struct target *target, int cpnum,
- uint32_t op, uint32_t CRm, uint64_t *value)
+ uint32_t op, uint32_t crm, uint64_t *value)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
@@ -75,11 +75,11 @@ static int dpm_mrrc(struct target *target, int cpnum,
return retval;
LOG_DEBUG("MRRC p%d, %d, r0, r1, c%d", cpnum,
- (int) op, (int) CRm);
+ (int)op, (int)crm);
/* read coprocessor register into R0, R1; return via DCC */
retval = dpm->instr_read_data_r0_r1(dpm,
- ARMV5_T_MRRC(cpnum, op, 0, 1, CRm),
+ ARMV5_T_MRRC(cpnum, op, 0, 1, crm),
value);
/* (void) */ dpm->finish(dpm);
@@ -112,7 +112,7 @@ static int dpm_mcr(struct target *target, int cpnum,
}
static int dpm_mcrr(struct target *target, int cpnum,
- uint32_t op, uint32_t CRm, uint64_t value)
+ uint32_t op, uint32_t crm, uint64_t value)
{
struct arm *arm = target_to_arm(target);
struct arm_dpm *dpm = arm->dpm;
@@ -123,11 +123,11 @@ static int dpm_mcrr(struct target *target, int cpnum,
return retval;
LOG_DEBUG("MCRR p%d, %d, r0, r1, c%d", cpnum,
- (int) op, (int) CRm);
+ (int)op, (int)crm);
/* read DCC into r0, r1; then write coprocessor register from R0, R1 */
retval = dpm->instr_write_data_r0_r1(dpm,
- ARMV5_T_MCRR(cpnum, op, 0, 1, CRm), value);
+ ARMV5_T_MCRR(cpnum, op, 0, 1, crm), value);
/* (void) */ dpm->finish(dpm);
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
index 31725ee544..c8ce51f299 100644
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -188,15 +188,15 @@
| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
/* Move to two ARM registers from coprocessor
- * CP: Coprocessor number
+ * cp: Coprocessor number
* op: Coprocessor opcode
- * Rt: destination register 1
- * Rt2: destination register 2
- * CRm: coprocessor source register
+ * rt: destination register 1
+ * rt2: destination register 2
+ * crm: coprocessor source register
*/
-#define ARMV5_T_MRRC(CP, op, Rt, Rt2, CRm) \
- (0xec500000 | (CRm) | ((op) << 4) | ((CP) << 8) \
- | ((Rt) << 12) | ((Rt2) << 16))
+#define ARMV5_T_MRRC(cp, op, rt, rt2, crm) \
+ (0xec500000 | (crm) | ((op) << 4) | ((cp) << 8) \
+ | ((rt) << 12) | ((rt2) << 16))
/* Move to coprocessor from ARM register
* cp: Coprocessor number
@@ -211,15 +211,15 @@
| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
/* Move to coprocessor from two ARM registers
- * CP: Coprocessor nunber
+ * cp: Coprocessor number
* op: Coprocessor opcode
- * Rt: destination register 1
- * Rt2: destination register 2
- * CRm: coprocessor source register
+ * rt: destination register 1
+ * rt2: destination register 2
+ * crm: coprocessor source register
*/
-#define ARMV5_T_MCRR(CP, op, Rt, Rt2, CRm) \
- (0xec400000 | (CRm) | ((op) << 4) | ((CP) << 8) \
- | ((Rt) << 12) | ((Rt2) << 16))
+#define ARMV5_T_MCRR(cp, op, rt, rt2, crm) \
+ (0xec400000 | (crm) | ((op) << 4) | ((cp) << 8) \
+ | ((rt) << 12) | ((rt2) << 16))
/* Breakpoint instruction (ARMv5)
* im: 16-bit immediate
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index d43ac50d73..0e4db23ea5 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1770,7 +1770,7 @@ static int arm_default_mrc(struct target *target, int
cpnum,
}
static int arm_default_mrrc(struct target *target, int cpnum,
- uint32_t op, uint32_t CRm,
+ uint32_t op, uint32_t crm,
uint64_t *value)
{
LOG_ERROR("%s doesn't implement MRRC", target_type_name(target));
@@ -1787,7 +1787,7 @@ static int arm_default_mcr(struct target *target, int
cpnum,
}
static int arm_default_mcrr(struct target *target, int cpnum,
- uint32_t op, uint32_t CRm,
+ uint32_t op, uint32_t crm,
uint64_t value)
{
LOG_ERROR("%s doesn't implement MCRR", target_type_name(target));
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 81bd40cc1b..8917bef323 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -487,8 +487,7 @@ static int cortex_a_instr_write_data_r0_r1(struct arm_dpm
*dpm,
return retval;
/* then the opcode, taking data from R0, R1 */
- retval = cortex_a_exec_opcode(
- a->armv7a_common.arm.target,
+ retval = cortex_a_exec_opcode(a->armv7a_common.arm.target,
opcode,
&dscr);
return retval;
--
