> On 24 Jul 2023, at 18:57, Tim Newsome <t...@sifive.com> wrote:
>
> As long as this is limited to cores that are known to maybe have such a bug
The proposal obviously apply to architectures that can identify legit
breakpoints.
In particular, for Cortex-M cores, that implement that set of FPB registers
storing breakpoint addresses, assuming that OpenOCD can read them.
All other architectures/cores can simply halt at the breakpoint, as they do now.
If necessary, this new behaviour can be enabled by a configuration option.
Liviu
