This is an automated email from Gerrit.
"Luca Hung <ychu...@nuvoton.com>" just uploaded a new patch set to Gerrit,
which you can find at https://review.openocd.org/c/openocd/+/7794
-- gerrit
commit d9a139b20980770256ca683659c0a9db7b3c25f9
Author: Luca Hung <ychu...@nuvoton.com>
Date: Mon Jul 31 15:08:18 2023 +0800
flash/nor: add support for Nuvoton NPCX4/K3 series flash
Added NPCX flash driver to support the Nuvoton NPCX4/K3 series
microcontrollers. Add config file for these series.
Change-Id: I0b6e128fa51146b561f422e23a98260594b1f138
Signed-off-by: Luca Hung <ychu...@nuvoton.com>
Signed-off-by: Mulin CHao <mlc...@nuvoton.com>
diff --git a/contrib/loaders/flash/npcx/npcx_algo.inc
b/contrib/loaders/flash/npcx/npcx_algo.inc
index 4312fdb1b4..46b79d8d9c 100644
--- a/contrib/loaders/flash/npcx/npcx_algo.inc
+++ b/contrib/loaders/flash/npcx/npcx_algo.inc
@@ -1,60 +1,70 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
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+0x01,0x9b,0x2b,0x70,0x19,0x0a,0x1b,0x0c,0x69,0x70,0xab,0x70,0xe8,0x70,0x23,0x7c,
+0x00,0x23,0x23,0x74,0x62,0x7c,0x63,0x74,0xa2,0x7c,0xa3,0x74,0xe2,0x7c,0xe3,0x74,
+0xdf,0xe7,0x60,0x68,0xa1,0x68,0xff,0xf7,0x65,0xff,0x00,0x28,0xef,0xd0,0x20,0x61,
+0xfe,0xe7,0xff,0xf7,0x9b,0xff,0xf8,0xe7,0x60,0x68,0xa1,0x68,0x2a,0x46,0xff,0xf7,
+0x1b,0xff,0xf2,0xe7,0x01,0x20,0xf2,0xe7,0x00,0x00,0x0c,0x20,0x14,0x00,0x0c,0x20,
+0xf0,0xb5,0x83,0x07,0x47,0xd0,0x54,0x1e,0x00,0x2a,0x41,0xd0,0x0d,0x06,0x2d,0x0e,
+0x02,0x00,0x03,0x26,0x02,0xe0,0x1a,0x00,0x01,0x3c,0x39,0xd3,0x53,0x1c,0x15,0x70,
+0x33,0x42,0xf8,0xd1,0x03,0x2c,0x2a,0xd9,0xff,0x22,0x0a,0x40,0x15,0x02,0x15,0x43,
+0x2a,0x04,0x15,0x43,0x0f,0x2c,0x14,0xd9,0x27,0x00,0x1a,0x00,0x10,0x3f,0x3e,0x09,
+0x01,0x36,0x36,0x01,0x9e,0x19,0x15,0x60,0x55,0x60,0x95,0x60,0xd5,0x60,0x10,0x32,
+0x96,0x42,0xf8,0xd1,0x0f,0x22,0x97,0x43,0x10,0x37,0xdb,0x19,0x14,0x40,0x03,0x2c,
+0x0d,0xd9,0x1a,0x00,0x27,0x1f,0xbe,0x08,0x01,0x36,0xb6,0x00,0x9e,0x19,0x20,0xc2,
+0xb2,0x42,0xfc,0xd1,0x03,0x22,0x97,0x43,0x04,0x37,0xdb,0x19,0x14,0x40,0x00,0x2c,
+0x06,0xd0,0x09,0x06,0x1c,0x19,0x09,0x0e,0x19,0x70,0x01,0x33,0x9c,0x42,0xfb,0xd1,
+0xf0,0xbc,0x02,0xbc,0x08,0x47,0x14,0x00,0x03,0x00,0xc3,0xe7,
diff --git a/contrib/loaders/flash/npcx/npcx_flash.c
b/contrib/loaders/flash/npcx/npcx_flash.c
index 7d59123aab..fe4f47f9d6 100644
--- a/contrib/loaders/flash/npcx/npcx_flash.c
+++ b/contrib/loaders/flash/npcx/npcx_flash.c
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2020 by Nuvoton Technology Corporation
@@ -10,9 +10,29 @@
#include <string.h>
#include "npcx_flash.h"
+/* flashloader parameter structure */
+__attribute__ ((section(".buffers.g_cfg")))
+volatile struct npcx_flash_params g_cfg;
+/* data buffer */
+__attribute__ ((section(".buffers.g_buf")))
+uint8_t g_buf[NPCX_FLASH_LOADER_BUFFER_SIZE];
+
/*----------------------------------------------------------------------------
* NPCX flash driver
*----------------------------------------------------------------------------*/
+static void flash_init(void)
+{
+ if (g_cfg.fiu_ver == NPCX_FIU_NPCK) {
+ /* Set pinmux to SHD flash */
+ NPCX_DEVCNT = 0x80;
+ NPCX_DEVALT(0) = 0xC0;
+ NPCX_DEVALT(4) = 0x00;
+ } else {
+ /* Avoid F_CS0 toggles while programming the internal flash. */
+ NPCX_SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
+ }
+}
+
static void flash_execute_cmd(uint8_t code, uint8_t cts)
{
/* Set UMA code */
@@ -26,11 +46,28 @@ static void flash_execute_cmd(uint8_t code, uint8_t cts)
static void flash_cs_level(uint8_t level)
{
+ int sw_cs = 0;
+
+ if (g_cfg.fiu_ver == NPCX_FIU_NPCX) {
+ sw_cs = 1;
+ } else if (g_cfg.fiu_ver == NPCX_FIU_NPCX_V2) {
+ sw_cs = 0;
+ } else if (g_cfg.fiu_ver == NPCX_FIU_NPCK) {
+ sw_cs = 1;
+ /* Unlock UMA before pulling down CS in NPCK series */
+ if (level) {
+ NPCX_CLEAR_BIT(NPCX_FIU_MSR_IE_CFG,
NPCX_FIU_MSR_IE_CFG_UMA_BLOCK);
+ } else {
+ NPCX_SET_BIT(NPCX_FIU_MSR_IE_CFG,
NPCX_FIU_MSR_IE_CFG_UMA_BLOCK);
+ }
+ }
+
/* Program chip select pin to high/low level */
- if (level)
- NPCX_SET_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
- else
- NPCX_CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1);
+ if (level) {
+ NPCX_SET_BIT(NPCX_UMA_ECTS, sw_cs);
+ } else {
+ NPCX_CLEAR_BIT(NPCX_UMA_ECTS, sw_cs);
+ }
}
static void flash_set_address(uint32_t dest_addr)
@@ -38,9 +75,9 @@ static void flash_set_address(uint32_t dest_addr)
uint8_t *addr = (uint8_t *)&dest_addr;
/* Set target flash address */
- NPCX_UMA_AB2 = addr[2];
- NPCX_UMA_AB1 = addr[1];
- NPCX_UMA_AB0 = addr[0];
+ NPCX_UMA_DB0 = addr[2];
+ NPCX_UMA_DB1 = addr[1];
+ NPCX_UMA_DB2 = addr[0];
}
void delay(uint32_t i)
@@ -104,7 +141,7 @@ static void flash_burst_write(uint32_t dest_addr, uint16_t
bytes,
/* Set write address */
flash_set_address(dest_addr);
/* Start programming */
- flash_execute_cmd(NPCX_CMD_FLASH_PROGRAM, NPCX_MASK_CMD_WR_ADR);
+ flash_execute_cmd(NPCX_CMD_FLASH_PROGRAM, NPCX_MASK_CMD_WR_3BYTE);
for (uint32_t i = 0; i < bytes; i++) {
flash_execute_cmd(*data, NPCX_MASK_CMD_WR_ONLY);
data++;
@@ -114,6 +151,15 @@ static void flash_burst_write(uint32_t dest_addr, uint16_t
bytes,
flash_cs_level(1);
}
+static void flash_get_stsreg(uint8_t *reg1, uint8_t *reg2)
+{
+ /* Read status register 1/2 for checking */
+ flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_RD_1BYTE);
+ *reg1 = NPCX_UMA_DB0;
+ flash_execute_cmd(NPCX_CMD_READ_STATUS_REG2, NPCX_MASK_CMD_RD_1BYTE);
+ *reg2 = NPCX_UMA_DB0;
+}
+
/* The data to write cannot cross 256 Bytes boundary */
static int flash_program_write(uint32_t addr, uint32_t size,
const uint8_t *data)
@@ -126,6 +172,40 @@ static int flash_program_write(uint32_t addr, uint32_t
size,
return flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
}
+int flash_physical_clear_stsreg(void)
+{
+ int status;
+ uint8_t reg1, reg2;
+
+ /* Read status register 1/2 for checking */
+ flash_get_stsreg(®1, ®2);
+ if (reg1 == 0x00 && reg2 == 0x00)
+ return NPCX_FLASH_STATUS_OK;
+
+ /* Enable write */
+ status = flash_write_enable();
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+ NPCX_UMA_DB0 = 0x0;
+ NPCX_UMA_DB1 = 0x0;
+
+ /* Write status register 1/2 */
+ flash_execute_cmd(NPCX_CMD_WRITE_STATUS_REG, NPCX_MASK_CMD_WR_2BYTE);
+
+ /* Wait writing completed */
+ status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+ /* Read status register 1/2 for checking */
+ flash_get_stsreg(®1, ®2);
+ if (reg1 != 0x00 || reg2 != 0x00)
+ return NPCX_FLASH_STATUS_FAILED;
+
+ return NPCX_FLASH_STATUS_OK;
+}
+
int flash_physical_write(uint32_t offset, uint32_t size, const uint8_t *data)
{
int status;
@@ -135,6 +215,13 @@ int flash_physical_write(uint32_t offset, uint32_t size,
const uint8_t *data)
uint32_t dest_addr = offset;
uint32_t write_len = ((trunk_start - offset) > size) ? size :
(trunk_start - offset);
+ /* Configure fiu and clear status registers if needed */
+ flash_init();
+ status = flash_physical_clear_stsreg();
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
+
if (write_len) {
status = flash_program_write(dest_addr, write_len, data);
if (status != NPCX_FLASH_STATUS_OK)
@@ -164,6 +251,14 @@ int flash_physical_write(uint32_t offset, uint32_t size,
const uint8_t *data)
int flash_physical_erase(uint32_t offset, uint32_t size)
{
+ /* Configure fiu */
+ flash_init();
+
+ /* clear flash status registers */
+ int status = flash_physical_clear_stsreg();
+ if (status != NPCX_FLASH_STATUS_OK)
+ return status;
+
/* Alignment has been checked in upper layer */
for (; size > 0; size -= NPCX_FLASH_ERASE_SIZE,
offset += NPCX_FLASH_ERASE_SIZE) {
@@ -175,7 +270,7 @@ int flash_physical_erase(uint32_t offset, uint32_t size)
/* Set erase address */
flash_set_address(offset);
/* Start erase */
- flash_execute_cmd(NPCX_CMD_SECTOR_ERASE, NPCX_MASK_CMD_ADR);
+ flash_execute_cmd(NPCX_CMD_SECTOR_ERASE,
NPCX_MASK_CMD_WR_3BYTE);
/* Wait erase completed */
status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
if (status != NPCX_FLASH_STATUS_OK)
@@ -187,53 +282,34 @@ int flash_physical_erase(uint32_t offset, uint32_t size)
int flash_physical_erase_all(void)
{
- /* Enable write */
- int status = flash_write_enable();
- if (status != NPCX_FLASH_STATUS_OK)
- return status;
-
- /* Start erase */
- flash_execute_cmd(NPCX_CMD_CHIP_ERASE, NPCX_MASK_CMD_ONLY);
+ int status;
- /* Wait erase completed */
- status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
+ /* Configure fiu and clear status register if needed */
+ flash_init();
+ status = flash_physical_clear_stsreg();
if (status != NPCX_FLASH_STATUS_OK)
return status;
- return NPCX_FLASH_STATUS_OK;
-}
-
-int flash_physical_clear_stsreg(void)
-{
/* Enable write */
- int status = flash_write_enable();
+ status = flash_write_enable();
if (status != NPCX_FLASH_STATUS_OK)
return status;
- NPCX_UMA_DB0 = 0x0;
- NPCX_UMA_DB1 = 0x0;
-
- /* Write status register 1/2 */
- flash_execute_cmd(NPCX_CMD_WRITE_STATUS_REG, NPCX_MASK_CMD_WR_2BYTE);
+ /* Start erase */
+ flash_execute_cmd(NPCX_CMD_CHIP_ERASE, NPCX_MASK_CMD_ONLY);
- /* Wait writing completed */
+ /* Wait erase completed */
status = flash_wait_ready(NPCX_FLASH_ABORT_TIMEOUT);
if (status != NPCX_FLASH_STATUS_OK)
return status;
- /* Read status register 1/2 for checking */
- flash_execute_cmd(NPCX_CMD_READ_STATUS_REG, NPCX_MASK_CMD_RD_1BYTE);
- if (NPCX_UMA_DB0 != 0x00)
- return NPCX_FLASH_STATUS_FAILED;
- flash_execute_cmd(NPCX_CMD_READ_STATUS_REG2, NPCX_MASK_CMD_RD_1BYTE);
- if (NPCX_UMA_DB0 != 0x00)
- return NPCX_FLASH_STATUS_FAILED;
-
return NPCX_FLASH_STATUS_OK;
}
int flash_get_id(uint32_t *id)
{
+ flash_init();
+
flash_execute_cmd(NPCX_CMD_READ_ID, NPCX_MASK_CMD_RD_3BYTE);
*id = NPCX_UMA_DB0 << 16 | NPCX_UMA_DB1 << 8 | NPCX_UMA_DB2;
@@ -254,30 +330,13 @@ uint32_t flashloader_init(struct npcx_flash_params
*params)
/*----------------------------------------------------------------------------
* Functions
*----------------------------------------------------------------------------*/
-/* flashloader parameter structure */
-__attribute__ ((section(".buffers.g_cfg")))
-volatile struct npcx_flash_params g_cfg;
-/* data buffer */
-__attribute__ ((section(".buffers.g_buf")))
-uint8_t g_buf[NPCX_FLASH_LOADER_BUFFER_SIZE];
-
int main(void)
{
- uint32_t id;
+ uint32_t id, status;
/* set buffer */
flashloader_init((struct npcx_flash_params *)&g_cfg);
- /* Avoid F_CS0 toggles while programming the internal flash. */
- NPCX_SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI);
-
- /* clear flash status registers */
- int status = flash_physical_clear_stsreg();
- if (status != NPCX_FLASH_STATUS_OK) {
- while (1)
- g_cfg.sync = status;
- }
-
while (1) {
/* wait command*/
while (g_cfg.sync == NPCX_FLASH_LOADER_WAIT)
diff --git a/contrib/loaders/flash/npcx/npcx_flash.h
b/contrib/loaders/flash/npcx/npcx_flash.h
index cc4f1ad506..48e5d82fd3 100644
--- a/contrib/loaders/flash/npcx/npcx_flash.h
+++ b/contrib/loaders/flash/npcx/npcx_flash.h
@@ -80,6 +80,7 @@
#define NPCX_FIU_DMM_CYC NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x032)
#define NPCX_FIU_EXT_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x033)
#define NPCX_FIU_UMA_AB0_3 NPCX_HW_DWORD(NPCX_FIU_BASE_ADDR + 0x034)
+#define NPCX_FIU_MSR_IE_CFG NPCX_HW_BYTE(NPCX_FIU_BASE_ADDR + 0x043)
/* FIU register fields */
#define NPCX_RESP_CFG_IAD_EN 0
@@ -93,6 +94,7 @@
#define NPCX_UMA_ECTS_SW_CS1 1
#define NPCX_UMA_ECTS_SEC_CS 2
#define NPCX_UMA_ECTS_UMA_LOCK 3
+#define NPCX_FIU_MSR_IE_CFG_UMA_BLOCK 3
/* Flash UMA commands for npcx internal SPI flash */
#define NPCX_CMD_READ_ID 0x9F
@@ -130,7 +132,6 @@
#define NPCX_SPI_FLASH_SR1_BUSY (1 << 0)
#define NPCX_MASK_CMD_ONLY (0xC0)
-#define NPCX_MASK_CMD_ADR (0xC0 | 0x08)
#define NPCX_MASK_CMD_ADR_WR (0xC0 | 0x20 | 0x08 | 0x01)
#define NPCX_MASK_RD_1BYTE (0xC0 | 0x10 | 0x01)
#define NPCX_MASK_RD_2BYTE (0xC0 | 0x10 | 0x02)
@@ -143,10 +144,12 @@
#define NPCX_MASK_CMD_WR_ONLY (0xC0 | 0x20)
#define NPCX_MASK_CMD_WR_1BYTE (0xC0 | 0x20 | 0x10 | 0x01)
#define NPCX_MASK_CMD_WR_2BYTE (0xC0 | 0x20 | 0x10 | 0x02)
-#define NPCX_MASK_CMD_WR_ADR (0xC0 | 0x20 | 0x08)
+#define NPCX_MASK_CMD_WR_3BYTE (0xC0 | 0x20 | 0x10 | 0x03)
+#define NPCX_MASK_CMD_WR_4BYTE (0xC0 | 0x20 | 0x10 | 0x04)
/* Flash loader parameters */
struct __attribute__((__packed__)) npcx_flash_params {
+ uint32_t fiu_ver; /* Flash controller unit version */
uint32_t addr; /* Address in flash */
uint32_t len; /* Number of bytes */
uint32_t cmd; /* Command */
@@ -176,4 +179,10 @@ enum npcx_flash_status {
NPCX_FLASH_STATUS_FAILED_TIMEOUT,
};
+enum npcx_fiu_ver {
+ NPCX_FIU_NPCX = 0,
+ NPCX_FIU_NPCX_V2,
+ NPCX_FIU_NPCK,
+};
+
#endif /* OPENOCD_LOADERS_FLASH_NPCX_NPCX_FLASH_H */
diff --git a/contrib/loaders/flash/npcx/npcx_flash_config.h
b/contrib/loaders/flash/npcx/npcx_flash_config.h
index 9ec1c5e331..4abd23e348 100644
--- a/contrib/loaders/flash/npcx/npcx_flash_config.h
+++ b/contrib/loaders/flash/npcx/npcx_flash_config.h
@@ -18,7 +18,7 @@
/* NPCX flash loader information */
#define NPCX_FLASH_LOADER_WORKING_ADDR 0x200C0000
#define NPCX_FLASH_LOADER_PARAMS_ADDR NPCX_FLASH_LOADER_WORKING_ADDR
-#define NPCX_FLASH_LOADER_PARAMS_SIZE 16
+#define NPCX_FLASH_LOADER_PARAMS_SIZE 20
#define NPCX_FLASH_LOADER_BUFFER_ADDR (NPCX_FLASH_LOADER_PARAMS_ADDR +
NPCX_FLASH_LOADER_PARAMS_SIZE)
#define NPCX_FLASH_LOADER_BUFFER_SIZE NPCX_FLASH_ERASE_SIZE
#define NPCX_FLASH_LOADER_PROGRAM_ADDR (NPCX_FLASH_LOADER_BUFFER_ADDR +
NPCX_FLASH_LOADER_BUFFER_SIZE)
diff --git a/src/flash/nor/npcx.c b/src/flash/nor/npcx.c
index bc84753463..7ce97188f1 100644
--- a/src/flash/nor/npcx.c
+++ b/src/flash/nor/npcx.c
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2020 by Nuvoton Technology Corporation
@@ -17,12 +17,11 @@
#include "../../../contrib/loaders/flash/npcx/npcx_flash.h"
/* NPCX flash loader */
-static const uint8_t npcx_algo[] = {
+const uint8_t npcx_algo[] = {
#include "../../../contrib/loaders/flash/npcx/npcx_algo.inc"
};
#define NPCX_FLASH_TIMEOUT_MS 8000
-#define NPCX_FLASH_BASE_ADDR 0x64000000
/* flash list */
enum npcx_flash_device_index {
@@ -44,6 +43,7 @@ struct npcx_flash_bank {
uint32_t algo_working_size;
uint32_t buffer_addr;
uint32_t params_addr;
+ uint32_t fiu_ver;
};
struct npcx_flash_info {
@@ -197,6 +197,7 @@ static enum npcx_flash_device_index
npcx_get_flash_id(struct flash_bank *bank, u
return retval;
/* Set up algorithm parameters for get flash ID command */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver,
npcx_bank->fiu_ver);
target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd,
NPCX_FLASH_CMD_GET_FLASH_ID);
target_buffer_set_u32(target, (uint8_t *)&algo_params.sync,
NPCX_FLASH_LOADER_WAIT);
@@ -250,6 +251,18 @@ static int npcx_probe(struct flash_bank *bank)
npcx_bank->buffer_addr = NPCX_FLASH_LOADER_BUFFER_ADDR;
npcx_bank->params_addr = NPCX_FLASH_LOADER_PARAMS_ADDR;
+ /* Select FIU version */
+ if (strcmp(bank->target->cmd_name, "npcx.cpu") == 0) {
+ npcx_bank->fiu_ver = NPCX_FIU_NPCX;
+ } else if (strcmp(bank->target->cmd_name, "npcx_v2.cpu") == 0) {
+ npcx_bank->fiu_ver = NPCX_FIU_NPCX_V2;
+ } else if (strcmp(bank->target->cmd_name, "npck.cpu") == 0) {
+ npcx_bank->fiu_ver = NPCX_FIU_NPCK;
+ } else {
+ LOG_ERROR("%s is not a valid target", bank->target->cmd_name);
+ return ERROR_TARGET_INVALID;
+ }
+
int retval = npcx_get_flash_id(bank, &flash_id);
if (retval != ERROR_OK)
return retval;
@@ -264,7 +277,6 @@ static int npcx_probe(struct flash_bank *bank)
return ERROR_FAIL;
}
- bank->base = NPCX_FLASH_BASE_ADDR;
bank->num_sectors = num_sectors;
bank->size = num_sectors * sector_length;
bank->write_start_alignment = 0;
@@ -341,6 +353,7 @@ static int npcx_chip_erase(struct flash_bank *bank)
return retval;
/* Set up algorithm parameters for chip erase command */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver,
npcx_bank->fiu_ver);
target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd,
NPCX_FLASH_CMD_ERASE_ALL);
target_buffer_set_u32(target, (uint8_t *)&algo_params.sync,
NPCX_FLASH_LOADER_WAIT);
@@ -397,6 +410,7 @@ static int npcx_erase(struct flash_bank *bank, unsigned int
first,
return retval;
/* Set up algorithm parameters for erase command */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver,
npcx_bank->fiu_ver);
target_buffer_set_u32(target, (uint8_t *)&algo_params.addr, address);
target_buffer_set_u32(target, (uint8_t *)&algo_params.len, length);
target_buffer_set_u32(target, (uint8_t *)&algo_params.cmd,
NPCX_FLASH_CMD_ERASE_SECTORS);
@@ -464,6 +478,7 @@ static int npcx_write(struct flash_bank *bank, const
uint8_t *buffer,
}
/* Update algo parameters for flash write */
+ target_buffer_set_u32(target, (uint8_t *)&algo_params.fiu_ver,
npcx_bank->fiu_ver);
target_buffer_set_u32(target, (uint8_t *)&algo_params.addr,
address);
target_buffer_set_u32(target, (uint8_t *)&algo_params.len,
size);
target_buffer_set_u32(target, (uint8_t *)&algo_params.sync,
NPCX_FLASH_LOADER_WAIT);
diff --git a/tcl/target/npcx.cfg b/tcl/target/npcx.cfg
index 1a21e1f7f5..276d69e1f5 100644
--- a/tcl/target/npcx.cfg
+++ b/tcl/target/npcx.cfg
@@ -9,7 +9,7 @@ source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
- set _CHIPNAME NPCX_M4
+ set _CHIPNAME npcx
}
# SWD DAP ID of Nuvoton NPCX Cortex-M4.
--
