This is an automated email from Gerrit.
"Karl Palsson <ka...@tweak.au>" just uploaded a new patch set to Gerrit, which
you can find at https://review.openocd.org/c/openocd/+/7845
-- gerrit
commit d9d1f598181815d9b6d3028b54dd4c7b22cf96bd
Author: Karl Palsson <ka...@tweak.au>
Date: Wed Aug 2 21:38:58 2023 +0000
target/cortex_m: check core implementor field
Presently, we only look at the Part Number field of the CPUID, and
completely ignore the Implmentor field, simply assuming it to be ARM.
Parts have since been found, with different implementors, that use
overlapping part numbers, causing detection to fail.
Include checks for the core implementor, and open up the part number to
be a plain integer, as we can no longer enumerate them.
Change-Id: Id81774f829104f57a0c105320d0d2e479fa01522
Signed-off-by: Karl Palsson <ka...@tweak.au>
diff --git a/src/target/arm.h b/src/target/arm.h
index fd61d5f514..f3abd6cbab 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -58,6 +58,11 @@ enum arm_arch {
ARM_ARCH_V8M,
};
+/** Known ARM implementor IDs */
+enum arm_implementor {
+ ARM_IMPLEMENTOR_ARM = 0x41,
+};
+
/**
* Represent state of an ARM core.
*
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 9541caa792..92af1ac7a7 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -50,63 +50,75 @@
/* Supported Cortex-M Cores */
static const struct cortex_m_part_info cortex_m_parts[] = {
{
+ .implementor = ARM_IMPLEMENTOR_ARM,
.partno = CORTEX_M0_PARTNO,
.name = "Cortex-M0",
.arch = ARM_ARCH_V6M,
},
{
+ .implementor = ARM_IMPLEMENTOR_ARM,
.partno = CORTEX_M0P_PARTNO,
.name = "Cortex-M0+",
.arch = ARM_ARCH_V6M,
},
{
+ .implementor = ARM_IMPLEMENTOR_ARM,
.partno = CORTEX_M1_PARTNO,
.name = "Cortex-M1",
.arch = ARM_ARCH_V6M,
},
{
+ .implementor = ARM_IMPLEMENTOR_ARM,
.partno = CORTEX_M3_PARTNO,
.name = "Cortex-M3",
.arch = ARM_ARCH_V7M,
.flags = CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
},
{
+ .implementor = ARM_IMPLEMENTOR_ARM,
.partno = CORTEX_M4_PARTNO,
.name = "Cortex-M4",
.arch = ARM_ARCH_V7M,
.flags = CORTEX_M_F_HAS_FPV4 | CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K,
},
{
+ .implementor = ARM_IMPLEMENTOR_ARM,
.partno = CORTEX_M7_PARTNO,
.name = "Cortex-M7",
.arch = ARM_ARCH_V7M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
+ .implementor = ARM_IMPLEMENTOR_ARM,
.partno = CORTEX_M23_PARTNO,
.name = "Cortex-M23",
.arch = ARM_ARCH_V8M,
},
{
+ .implementor = ARM_IMPLEMENTOR_ARM,
.partno = CORTEX_M33_PARTNO,
.name = "Cortex-M33",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
+ .implementor = ARM_IMPLEMENTOR_ARM,
.partno = CORTEX_M35P_PARTNO,
.name = "Cortex-M35P",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
+ .implementor = ARM_IMPLEMENTOR_ARM,
.partno = CORTEX_M55_PARTNO,
.name = "Cortex-M55",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
},
{
- .partno = STAR_MC1_PARTNO,
+ /* FIXME: VERIFY! */
+ .implementor = ARM_IMPLEMENTOR_ARM,
+ .partno = 0x132,
.name = "STAR-MC1",
.arch = ARM_ARCH_V8M,
.flags = CORTEX_M_F_HAS_FPV5,
@@ -2533,17 +2545,19 @@ int cortex_m_examine(struct target *target)
return retval;
/* Get ARCH and CPU types */
- const enum cortex_m_partno core_partno = (cpuid &
ARM_CPUID_PARTNO_MASK) >> ARM_CPUID_PARTNO_POS;
+ const int core_impl = (cpuid & ARM_CPUID_IMPLEMENTOR_MASK) >>
ARM_CPUID_IMPLEMENTOR_POS;
+ const int core_partno = (cpuid & ARM_CPUID_PARTNO_MASK) >>
ARM_CPUID_PARTNO_POS;
for (unsigned int n = 0; n < ARRAY_SIZE(cortex_m_parts); n++) {
- if (core_partno == cortex_m_parts[n].partno) {
+ if (core_impl == cortex_m_parts[n].implementor
+ && core_partno == cortex_m_parts[n].partno) {
cortex_m->core_info = &cortex_m_parts[n];
break;
}
}
if (!cortex_m->core_info) {
- LOG_TARGET_ERROR(target, "Cortex-M PARTNO 0x%x is
unrecognized", core_partno);
+ LOG_TARGET_ERROR(target, "Cortex-M Implementor: 0x%x,
PARTNO 0x%x is unrecognized", core_impl, core_partno);
return ERROR_FAIL;
}
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index a1c43b56de..077a1fa00e 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -31,12 +31,18 @@
#define CPUID 0xE000ED00
+#define ARM_CPUID_IMPLEMENTOR_POS 24
+#define ARM_CPUID_IMPLEMENTOR_MASK (0xff << ARM_CPUID_IMPLEMENTOR_POS)
#define ARM_CPUID_PARTNO_POS 4
#define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS)
+/** ARM assigned core part ids.
+ * Only list the _ARM_ assigned fields here.
+ * This is unfortunately used as a heuristic stand in for vendor part ids
+ * in some flash drivers.
+ */
enum cortex_m_partno {
CORTEX_M_PARTNO_INVALID,
- STAR_MC1_PARTNO = 0x132,
CORTEX_M0_PARTNO = 0xC20,
CORTEX_M1_PARTNO = 0xC21,
CORTEX_M3_PARTNO = 0xC23,
@@ -55,7 +61,8 @@ enum cortex_m_partno {
#define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2)
struct cortex_m_part_info {
- enum cortex_m_partno partno;
+ int implementor;
+ int partno;
const char *name;
enum arm_arch arch;
uint32_t flags;
@@ -296,7 +303,7 @@ target_to_cortex_m_safe(struct target *target)
* or CORTEX_M_PARTNO_INVALID if the magic number does not match
* or core_info is not initialised.
*/
-static inline enum cortex_m_partno cortex_m_get_partno_safe(struct target
*target)
+static inline int cortex_m_get_partno_safe(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target);
if (!cortex_m)
--
