[PATCH]: 29df9ad922 tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access

[gerrit]

This is an automated email from Gerrit.

"Nishanth Menon <n...@ti.com>" just uploaded a new patch set to Gerrit, which 
you can find at https://review.openocd.org/c/openocd/+/7899

-- gerrit

commit 29df9ad922f3be175dbe5525eab302c77c6e3dc4
Author: Nishanth Menon <n...@ti.com>
Date:   Thu Sep 14 07:49:02 2023 -0500

    tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access
    
    While we can read and write from memory from the view of various
    processors, All K3 debug systems have a AXI Access port that allows
    us to directly access memory from debug interface. This port is esp
    useful in the following scenarios:
    
    1. Debug cache related behavior on processors as this provides a
       direct bypass path.
    2. Processor has crashed or inaccessible for some reason (low power
       state etc.)
    3. Scenarios prior to the processor getting active.
    4. Debug MMU or address translation issues (example: TI's Region
       Address Table {RAT} translation table used to physically map
       SoC address space into R5/M4F processor address space)
    
    The AXI-AP port is the same for all processors in TI's K3 family.
    
    Change-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b
    Reported-by: Dubravko Srsan <dubravko.sr...@dolotron.com>
    Signed-off-by: Nishanth Menon <n...@ti.com>

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 2ba6ab34f3..246933bb43 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -228,6 +228,9 @@ set _TARGETNAME $_CHIPNAME.cpu
 
 set _CTINAME $_CHIPNAME.cti
 
+# AXI AP access port for SoC address map
+target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num 2
+
 # sysctrl is always present
 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex 
$CM3_CTIBASE 0]
 

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