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"Walter J. <walter...@oss.cipunited.com>" just uploaded a new patch set to
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7905
-- gerrit
commit e4100e8326f11def02eaab51bf42bfc99d0a11f8
Author: Walter Ji <walter...@oss.cipunited.com>
Date: Fri Sep 22 13:16:51 2023 +0800
target/mips32: update coprocessor 0 command
Update mips32 cp0 command, it accetps cp0 reg names now.
Change-Id: Ib23dd13519def77a657c9c5bb039276746207b9b
Signed-off-by: Walter Ji <walter...@oss.cipunited.com>
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 0553bcda4a..af2b11d8c7 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -1380,15 +1380,99 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
}
/* two or more argument, access a single register/select (write if
third argument is given) */
- if (CMD_ARGC < 2)
- return ERROR_COMMAND_SYNTAX_ERROR;
- else {
- uint32_t cp0_reg, cp0_sel;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
+ if (CMD_ARGC < 2) {
+ uint32_t value;
+
+ if (CMD_ARGC == 0) {
+ for (int i = 0; i < MIPS32NUMCP0REGS; i++) {
+ if (mips32_cp0_regs[i].core & mips32->cp0_mask)
{
+ retval = mips32_cp0_read(ejtag_info,
&value, mips32_cp0_regs[i].reg, mips32_cp0_regs[i].sel);
+ if (retval != ERROR_OK) {
+ command_print(CMD, "couldn't
access reg %s", mips32_cp0_regs[i].name);
+ return ERROR_OK;
+ }
+ } else {
+ /* Register name not valid for this
core */
+ continue;
+ }
+ command_print(CMD, "%*s: 0x%8.8x", 14,
mips32_cp0_regs[i].name, value);
+ }
+ } else {
+ for (int i = 0; i < MIPS32NUMCP0REGS; i++) {
+ /* find register name */
+ if (mips32_cp0_regs[i].core & mips32->cp0_mask)
{
+ if (strcmp(mips32_cp0_regs[i].name,
CMD_ARGV[0]) == 0) {
+ retval =
mips32_cp0_read(ejtag_info, &value, mips32_cp0_regs[i].reg,
mips32_cp0_regs[i].sel);
+ command_print(CMD, "0x%8.8x",
value);
+ if (retval != ERROR_OK)
+ LOG_INFO("Encounter an
Error while reading cp0 reg %d sel %d",
+
mips32_cp0_regs[i].reg, mips32_cp0_regs[i].sel);
+ return ERROR_OK;
+ }
+ } else {
+ /* Register name not valid for this
core */
+ continue;
+ }
+ }
+
+ LOG_ERROR("BUG: register '%s' not found", CMD_ARGV[0]);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ } else {
if (CMD_ARGC == 2) {
uint32_t value;
+ int tmp = *CMD_ARGV[0];
+
+ if (isdigit(tmp) == false) {
+ for (int i = 0; i < MIPS32NUMCP0REGS; i++) {
+ /* find register name */
+ if (mips32_cp0_regs[i].core &
mips32->cp0_mask) {
+ if
(strcmp(mips32_cp0_regs[i].name, CMD_ARGV[0]) == 0) {
+ uint32_t cp0_reg =
mips32_cp0_regs[i].reg;
+ uint32_t cp0_sel =
mips32_cp0_regs[i].sel;
+
+
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
+
+ /* Check if user is
writing to Status register */
+ if (cp0_reg ==
MIPS32_C0_STATUS && cp0_sel == 0) {
+
mips32->core_regs.cp0[MIPS32_REG_C0_STATUS_INDEX] = value;
+
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_STATUS_INDEX].dirty = 1;
+ } else if (cp0_reg ==
MIPS32_C0_CAUSE && cp0_sel == 0) {
+ /* Cause
register ?? Update register cache with new value */
+
mips32->core_regs.cp0[MIPS32_REG_C0_CAUSE_INDEX] = value;
+
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_CAUSE_INDEX].dirty = 1;
+ } else if (cp0_reg ==
MIPS32_C0_DEPC && cp0_sel == 0) {
+ /* DEPC ?
Update cached PC */
+
mips32->core_regs.cp0[MIPS32_REG_C0_PC_INDEX] = value;
+
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = 1;
+ } else if (cp0_reg ==
MIPS32_C0_GUESTCTL1 && cp0_sel == 4) {
+ /* guestCtl1 ?
Update it */
+
mips32->core_regs.cp0[MIPS32_REG_C0_GUESTCTL1_INDEX] = value;
+
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_GUESTCTL1_INDEX].dirty = 1;
+ }
+
+ retval =
mips32_cp0_write(ejtag_info, value,
+
mips32_cp0_regs[i].reg,
+
mips32_cp0_regs[i].sel);
+ if (retval != ERROR_OK)
+
LOG_INFO("Encounter an Error while writing to cp0 reg %d, sel %d",
+
mips32_cp0_regs[i].reg, mips32_cp0_regs[i].sel);
+ return ERROR_OK;
+ }
+ } else {
+ /* Register name not valid for
this core */
+ continue;
+ }
+ }
+
+ LOG_ERROR("BUG: register '%s' not found",
CMD_ARGV[0]);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ uint32_t cp0_reg, cp0_sel;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
retval = mips32_cp0_read(ejtag_info, &value, cp0_reg,
cp0_sel);
if (retval != ERROR_OK) {
@@ -1401,8 +1485,31 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
cp0_reg, cp0_sel, value);
} else if (CMD_ARGC == 3) {
+ uint32_t cp0_reg, cp0_sel;
uint32_t value;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
+
+ /* Check if user is writing to Status register */
+ if (cp0_reg == MIPS32_C0_STATUS && cp0_sel == 0) {
+
mips32->core_regs.cp0[MIPS32_REG_C0_STATUS_INDEX] = value;
+
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_STATUS_INDEX].dirty = 1;
+ } else if (cp0_reg == MIPS32_C0_CAUSE && cp0_sel == 0) {
+ /* Cause register ?? Update register cache with
new value */
+
mips32->core_regs.cp0[MIPS32_REG_C0_CAUSE_INDEX] = value;
+
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_CAUSE_INDEX].dirty = 1;
+ } else if (cp0_reg == MIPS32_C0_DEPC && cp0_sel == 0) {
+ /* DEPC ? Update cached PC */
+ mips32->core_regs.cp0[MIPS32_REG_C0_PC_INDEX] =
value;
+
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = 1;
+ } else if (cp0_reg == MIPS32_C0_GUESTCTL1 && cp0_sel ==
4) {
+ /* guestCtl1 ? Update it */
+
mips32->core_regs.cp0[MIPS32_REG_C0_GUESTCTL1_INDEX] = value;
+
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_GUESTCTL1_INDEX].dirty = 1;
+ }
+
retval = mips32_cp0_write(ejtag_info, value, cp0_reg,
cp0_sel);
if (retval != ERROR_OK) {
command_print(CMD,
@@ -2082,7 +2189,7 @@ static const struct command_registration
mips32_exec_command_handlers[] = {
.name = "cp0",
.handler = mips32_handle_cp0_command,
.mode = COMMAND_EXEC,
- .usage = "regnum select [value]",
+ .usage = "[[reg_name|regnum select] [value]]",
.help = "display/modify cp0 register",
},
{
--
