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"Ian Thompson <ia...@cadence.com>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/7973

-- gerrit

commit 2db27311858d7db8bafbfca766184cccb5a75911
Author: ianst <ia...@cadence.com>
Date:   Fri Oct 20 14:12:12 2023 -0700

    xtensa: update XDM register map for TRAX support
    
    - Include additional debug module registers
    - Add translation function for DM reg addr -> ID
    
    Signed-off-by: ianst <ia...@cadence.com>
    Change-Id: If95419d24a9f27a40fa695c8c15326cdfd127ef1

diff --git a/src/target/xtensa/xtensa_debug_module.c 
b/src/target/xtensa/xtensa_debug_module.c
index 31d7a9435c..fbe4bca8a6 100644
--- a/src/target/xtensa/xtensa_debug_module.c
+++ b/src/target/xtensa/xtensa_debug_module.c
@@ -34,6 +34,16 @@ static const struct xtensa_dm_pwr_reg_offsets 
xdm_pwr_regs[XDMREG_PWRNUM] =
 static const struct xtensa_dm_reg_offsets xdm_regs[XDMREG_NUM] =
        XTENSA_DM_REG_OFFSETS;
 
+enum xtensa_dm_reg xtensa_dm_regaddr_to_id(uint32_t addr)
+{
+       enum xtensa_dm_reg id;
+       uint32_t addr_masked = (addr & (XTENSA_DM_APB_ALIGN - 1));
+       for (id = XDMREG_TRAXID; id < XDMREG_NUM; id++)
+               if (xdm_regs[id].apb == addr_masked)
+                       break;
+       return id;
+}
+
 static void xtensa_dm_add_set_ir(struct xtensa_debug_module *dm, uint8_t value)
 {
        struct scan_field field;
diff --git a/src/target/xtensa/xtensa_debug_module.h 
b/src/target/xtensa/xtensa_debug_module.h
index 46b29354cd..89c0defd88 100644
--- a/src/target/xtensa/xtensa_debug_module.h
+++ b/src/target/xtensa/xtensa_debug_module.h
@@ -75,6 +75,22 @@ enum xtensa_dm_reg {
        XDMREG_DELAYCNT,
        XDMREG_MEMADDRSTART,
        XDMREG_MEMADDREND,
+       XDMREG_EXTTIMELO,
+       XDMREG_EXTTIMEHI,
+       XDMREG_TRAXRSVD48,
+       XDMREG_TRAXRSVD4C,
+       XDMREG_TRAXRSVD50,
+       XDMREG_TRAXRSVD54,
+       XDMREG_TRAXRSVD58,
+       XDMREG_TRAXRSVD5C,
+       XDMREG_TRAXRSVD60,
+       XDMREG_TRAXRSVD64,
+       XDMREG_TRAXRSVD68,
+       XDMREG_TRAXRSVD6C,
+       XDMREG_TRAXRSVD70,
+       XDMREG_TRAXRSVD74,
+       XDMREG_CONFIGID0,
+       XDMREG_CONFIGID1,
 
        /* Performance Monitor Registers */
        XDMREG_PMG,
@@ -168,6 +184,22 @@ struct xtensa_dm_reg_offsets {
        { .nar = 0x07, .apb = 0x001c }, /* XDMREG_DELAYCNT */           \
        { .nar = 0x08, .apb = 0x0020 }, /* XDMREG_MEMADDRSTART */       \
        { .nar = 0x09, .apb = 0x0024 }, /* XDMREG_MEMADDREND */         \
+       { .nar = 0x10, .apb = 0x0040 }, /* XDMREG_EXTTIMELO */          \
+       { .nar = 0x11, .apb = 0x0044 }, /* XDMREG_EXTTIMEHI */          \
+       { .nar = 0x12, .apb = 0x0048 }, /* XDMREG_TRAXRSVD48 */         \
+       { .nar = 0x13, .apb = 0x004c }, /* XDMREG_TRAXRSVD4C */         \
+       { .nar = 0x14, .apb = 0x0050 }, /* XDMREG_TRAXRSVD50 */         \
+       { .nar = 0x15, .apb = 0x0054 }, /* XDMREG_TRAXRSVD54 */         \
+       { .nar = 0x16, .apb = 0x0058 }, /* XDMREG_TRAXRSVD58 */         \
+       { .nar = 0x17, .apb = 0x005c }, /* XDMREG_TRAXRSVD5C */         \
+       { .nar = 0x18, .apb = 0x0060 }, /* XDMREG_TRAXRSVD60 */         \
+       { .nar = 0x19, .apb = 0x0064 }, /* XDMREG_TRAXRSVD64 */         \
+       { .nar = 0x1a, .apb = 0x0068 }, /* XDMREG_TRAXRSVD68 */         \
+       { .nar = 0x1b, .apb = 0x006c }, /* XDMREG_TRAXRSVD6C */         \
+       { .nar = 0x1c, .apb = 0x0070 }, /* XDMREG_TRAXRSVD70 */         \
+       { .nar = 0x1d, .apb = 0x0074 }, /* XDMREG_TRAXRSVD74 */         \
+       { .nar = 0x1e, .apb = 0x0078 }, /* XDMREG_CONFIGID0 */          \
+       { .nar = 0x1f, .apb = 0x007c }, /* XDMREG_CONFIGID1 */          \
                                                                                
                                                \
        /* Performance Monitor Registers */                                     
                \
        { .nar = 0x20, .apb = 0x1000 }, /* XDMREG_PMG */                        
\
@@ -297,6 +329,11 @@ struct xtensa_dm_reg_offsets {
 #define DEBUGCAUSE_DI               BIT(5)     /* Debug Interrupt */
 #define DEBUGCAUSE_VALID            BIT(31)    /* Pseudo-value to trigger 
reread (NX only) */
 
+/* TRAXID */
+#define TRAXID_PRODNO_TRAX          0          /* TRAXID.PRODNO value for TRAX 
module */
+#define TRAXID_PRODNO_SHIFT         28
+#define TRAXID_PRODNO_MASK          0xf
+
 #define TRAXCTRL_TREN               BIT(0)     /* Trace enable. Tracing starts 
on 0->1 */
 #define TRAXCTRL_TRSTP              BIT(1)     /* Trace Stop. Make 1 to stop 
trace. */
 #define TRAXCTRL_PCMEN              BIT(2)     /* PC match enable */
@@ -464,6 +501,7 @@ struct xtensa_debug_module {
        uint32_t ap_offset;
 };
 
+enum xtensa_dm_reg xtensa_dm_regaddr_to_id(uint32_t addr);
 int xtensa_dm_init(struct xtensa_debug_module *dm, const struct 
xtensa_debug_module_config *cfg);
 void xtensa_dm_deinit(struct xtensa_debug_module *dm);
 int xtensa_dm_poll(struct xtensa_debug_module *dm);

-- 

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